I agree with Larry about the time-of-flight issue. It's quite
important. This method may not be as effective as it first sounds.
As you scale up the dielectric constant, the capacitance per square
goes up proportional to Er, but the radius of the "disk" of
effective capacitance surrounding your component shrinks.
The interplane capacitance has to near the driver, to within a
small fraction of a risetime, in order to be effective.
At very high speeds, only a small disk of
interplane capacitance is doing most of the work for each chip.
In a high-speed design, the radius of the effective
capacitive disk shrinks as 1/sqrt(Er),
therefore the area of the effective capacitance shrinks
as 1/Er, therefore the total amount of capacitance (C per square
inch times the area of the effective disk) remains constant.
Once you are going fast enough that the board no longer
acts as a lumped circuit, scaling up the dielectric
constant doesn't help. (For boards small enough to be
considered a lumped-element system, increasing the dielectric
On another issue brought up by Eric, you may run into some
peculiar resonance effects with this design. The whole power
and ground system will support several resonant modes.
Viewing the power-ground planes themselves as a huge, fat
transmission line, the first mode of resonance will
occur at a cycle time corresponding to one round-trip
propagation delay from one side of the board to the other
If the board is, say, 6 inches x 6 inches, then
this first resonant mode will occur at time:
Tresonance = 2 * W * DelayPerInch = 36,062 ps
Where W is the board width (6 inches)
and DelayPerInch = 85 ps/inch * sqrt(Er=5000) = 6010 ps/inch
The resonant frequeny, Fresonance = 1/Tresonance = 28 MHz.
If your circuits demand significant currents from the power
system at at repetitive frequency of 28 MHz (or a multiple
thereof), the bypassing system will prove to be ineffective.
Regarding Eric Wheatley's comments, I don't see how dividing
the planes into multiple patches of capacitance will
really help very much. You'll still have a coupled network
of capacitors, which will still support a rather low-frequency
resonant mode. With normal bypass capacitors, the (rather substantial)
lead inductance of the parts prevents such wierd resonance
effects from taking hold. Here that effect doesn't help.
It's probably important to take a look at the Q of the power
system resonance. For ordinary dielectrics (FR-4), the first
mode is up in the 500 MHz range, and the Q is only 4 to 8, so
it doesn't cause that much of a problem. The primary loss factor
in a normal board (as far as I can tell) is the skin effect
resistance of the copper planes, with a little help from
In Elya's case, the skin effect isn't going to help as much
(because the first resonance is a lot lower). Elya, can
you tell us what is the loss tangent of your material?
Has anybody got some real-life measurements of this stuff?
Dr. Howard Johnson
At 09:58 PM 6/15/98 +2, you wrote:
a) High Permittivity Dielectrics
We are considering to use, for RF and ultra-high speed digital circuits,
very high permittivity dielectrics between the PCBs ("Thick Film
Assume a separation between GND and VCC of 1.6mil, and a dielectric
constant Epsilon(r) of 5,000.
We have calculated that for a sq. Inch of PCB this is "worth" about 700nF
In this case, would discrete decoupling capacitors actually be necessary,
would they be of any avail or perhaps even the opposite? Any input on
this will be greatly appreciated.
b) Analog Circuit Decoupling
Does anyone know any "rule of thumb" for selecting the proper value of
decoupling capacitors for <underline>analog circuits</underline>? In
digital circuits - the rise time and switching currents of the devices
play an important role... What are the considerations in Analog
Any reply to either or both questions will be greatly appreciated.
Elya B. Joffe - EMC Engineer
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