[SI-LIST] : tying clock outputs to reduce skew?
Wed, 15 Apr 1998 12:55:54 -0700
We're thinking about tying some or all of the 100MHz outputs of a
Motorola MPC952 clock generator together into a single node, and
distributing a clock from there to various loads via series
terminator. The idea is to eliminate output-to-output skew by
combining all into a single waveform. I think that if the inter-output
traces are kept short enough, it ought to behave as a passive mixer of
all the clocks. Motorola has heard of this being done, but has no
advice to offer.
One hazard is that a voltage differential exists between skewed
outputs during edges, giving rise to a small current flow out of one
pin into another, but I think this should be small.
Can any si-list experts offer advice on this technique?