Re: [SI-LIST] : Substrate modeling and analysis tool

Xavier Aragones (aragones@eel.upc.es)
Tue, 11 Nov 1997 17:25:40 +0000

>Hello SI group,
>
>I would like to hear from anyone who has experience in substrate modeling;
>I would like to know which analysis tools are used and their pros and cons.
>Especially if anyone has used a tool called LAYIN from Snaketech, I would
>appreciate your input.
>
>Thank you,
>
>Soon Young Lee
>Harris Semiconductor

The only tool I tested is SUBSPACE (available at
http://dutentb.et.tudelft.nl/research/space.html). It extracts a SPICE
resistive model between all terminals in a layout. I used it more than
a year ago, and it was very slow. A number of versions have been released
in this time, with a number of improvements and speed =A1ncrease, but I
haven't gone back to it.

About LAYIN, the only information I have is from the web site
(www.snaketech.com), and the papers published at IEEE CICC'94 and PATMOS'95=
.
It uses finite difference methods, so the computation time should dramatical=
ly
increase with the circuit complexity, although the publicity in the web site
claims it's fast. I would also appreciate benchmarks if anybody has used it.
An advantage of this tool is accurate well treatment.

People at Berkeley and Carnegie Mellon have also developed tools and
published papers, but as far as I know they are not available. I can
post you my list of references, if you're interested. I'm also aware
that Cadence is working on substrate modeling, more inputs would again
be appreciated.

Regards,

____________________________________________________________________________

O O O D Xavier Aragones
O O O E Departament d'Enginyeria Electronica
O O O E Universitat Politecnica de Catalunya (UPC)
U P C Modul C4, Campus Nord, c/ Gran Capita, s/n
08034 BARCELONA (Spain)

phone. + 34 3 4017482 e-mail: aragones@eel.upc.es
fax. + 34 3 4016756 http://www-eel.upc.es
____________________________________________________________________________