Re: [SI-LIST] : Signal Integrity of 500 MHz on PCB

RICHARD_BRUSH@hp-santaclara-om3.om.hp.com
Thu, 6 Nov 97 12:22:33 -0800

Yes, I have designed boards with ECLinPS logic at 500 MHz clock rates.
I used a transmission line simulator (LineSim by Hyperlynx) to
optimize the clock tree, PCB stackup, routing and terminations.
Measured waveforms and signal delays were virtually identical to
simulated values. I offer the following suggestions:

1. Use a multi-layer PCB. In addition to power and GND planes, use a
dedicated internal layer for clock distribution, preferably next to a
GND layer for good impedance control and low EMI.

2. Use a clock buffer or driver with separate outputs for each load.
This makes it much easier to avoid clock glitches at the loads due to
reflections, and to adjust the clock delay for individual loads.

3. Pay close attention to layout. Reduce critical timing paths by
placing associated components as close together as possible. Minimize
overall circuit dimensions. (I have had no problems on FR-4 for clock
lengths up to 6".)

4. Design clock traces for the same impedance on the internal layer as
well as the external layer(s) where components are located. This
minimizes reflections at vias between layers.

5. Provide a GND via close to any clock signal via. This provides a
low impedance (small "loop area") path for return currents where the
signal passes between layers.

6. Terminate every clock trace properly. In general either series (at
the driver) or parallel (at the load) may be used, but not both. Place
the series resistor (if used) on the component side as close to the
driver as possible, between the driver pin and a via to an internal
clock trace. Place the parallel resistor (if used) at the farthest end
of the line, beyond the load. If a parallel RC is used connect the C to
GND, not to the signal. Avoid branching or "stubs" on a clock net.

7. Make low impedance connections between GND, power and ICs. Use
separate vias for each GND or power pin on a device. Place the via as
close to the pin as possible and use the shortest, widest trace to
connect the via to the device pin pad. (Some PCB boards actually have
vias under pins, although this may violate some PCB design rules.)

8. Clock driver ICs and parallel termination should be bypassed with
caps that are effective at clock frequencies. I have had good results
selecting a cap with the self resonant frequency (minimum impedance)
near or somewhat higher than the clock fundamental frequency. For your
case that means a 1206 or (preferably) 0805 size about 50-100pf in
value. A good web resource is www.avxcorp.com. Go to "technical
information", then "online software", then "SPICAP" for a program that
calulates capacitor frequency response.

9. An excellent reference book for high speed designs is the Motorola
"MECL Design Handbook". (This is not the same as the MECL Databook).

______________________________ Reply Separator _________________________________
Subject: [SI-LIST] : Signal Integrity of 500 MHz on PCB
Author: Non-HP-csoolan (csoolan@dso.org.sg) at HP-Boise,mimegw18
Date: 11/6/97 4:34 PM


Hello,

I would just like to check with anyone who has done any discrete components
design
that uses 500 MHz clock. This translates to a 2ns period and a risetime
of less than
0.5 ns. Does anyone know if this high speed design will work on a normal
8 layer
FR4 board or any suggestions and comments are greatly appreciated. We did
ran some
simulation using PNC signal integrity and apparent it did not show very
optimistic results.

Thanks in advance.










******************************************************************************
Cheah Soo Lan
DSO NATIONAL LAB.
20 SCIENCE PARK DRIVE
SINGAPORE 118 230

EMAIL: csoolan@dso.org.sg