RE: [SI-LIST] : Excessive clock overshoot

Andrew Ingraham (Andrew.Ingraham@digital.com)
Thu, 14 May 1998 09:47:56 -0400

> Would the resonance be caused by the internal clock circuitry or the
> load
> it's driving?

I expect that it is the load, but it could be the source package too, or
both.

Your terminations don't match the main bus's impedance, so there will be
reflections; and when there are reflections back and forth, there are
resonances. I think D. C. Sessions hinted the same.

You said there are stubs, so even if the main bus were matched,
reflections from the stubs are inevitable.

If I understand your configuration, the buffer drives a heavily loaded
backplane with stubs, implying there are multiple loads distributed
along the bus. How did you intend to avoid non-monotonic edges? Unless
the driver is strong enough to drive full swings directly into your 25
ohm bus ( = incident-wave switching, and then you must terminate it well
to avoid nasty overshoot and reflections), then there will be plateaus
and possible non-monotonic edges at intermediate points along the bus.

If the spacing between stubs/loads is comparable to the risetime, that's
another factor too.

Also, you say there are terminations at both ends of the bus. Does this
mean the clock driver is in the middle of the bus? If so, it drives
12.5 ohms for the first few nanoseconds. If the driver is strong
enough, initially it dumps a hefty current step onto the bus, which
reflects back and doubles (quadruples?) the initial voltage step.

Regards,
Andy