Re: [SI-LIST] : BGA Ni-Au platting pattern.
Fred Balistreri (email@example.com)
Wed, 07 Oct 1998 08:22:36 -0700
Gregory P. Fitzgerald wrote:
> I assume you re talking about the plating bar (stub) that goes out to the
> edge of the package. Most tools that I know of do not consider this in
> their electrical extraction however Advanced Packaging Ensemble from
> Cadence does.
> When the solver/extractor in SPECCTRAQuest sees the 'T-point' created, it
> builds the plating bar stub as a transmission line that is open ended.
> Based on the package correlation (measurement) work I did when supporting
> the Alpha processsor and its core logic ASICs at Digital, the effect of the
> stub (the additional capacitive loading, the reflection caused by the open
> ended T-line,etc.) seemed to be negligble above ~1 nS edge rates, but
> noticeable at 0.75 nS and below.
> With a good extractor that 'does the right thing' you can easily verify
> when you need to consider: a) the effects of the stub and take them into
> account and/or b)the effect of 'pin-swapping' a short trace/long stub net
> for a long trace/no stub trace.
> At 03:49 PM 10/7/98 +0900, komerix wrote:
> >Hello All,
> >I am simulating BGA platting patterns.
> >In my thought, there aren't any tools that could condsider plating patterns.
> >I also modeled this patterns with one material, copper.
> >But, I can't affirm that this would have litttle error.
> >Could anyone tell me how much deviations exist between measurement and
> >simulation result?
> >I will appreciate any information about this.
> >Sunhue HUH
> >## Komerix Engineering. ##
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> Greg Fitzgerald
> Cadence Design Systems
> Performance Engineering Business Unit
> 270 Chelmsford, MA 01824
> Phone: 978-446-6638
> FAX: 978-446-6798
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Applied Simulation Technology considers these type of stubs in
packaging application. The tools also can write out IBIS models of the
package as well as simulating the electrical characteristics. The
package is call ApsimIBIS-LCR.
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