RE: [SI-LIST] : A timing question in high speed bus

Scott McMorrow ([email protected])
Wed, 18 Nov 1998 14:06:29 -0800

Vinu has correctly pointed out that for the SN74GTL16622 the timing
specifications are under a loading condition of 30 pF. This will,
of course, change the timing budget that I presented previously.
My simulations for this device indicate that there is a
400ps rising edge/450 ps falling edge (slow corner)
correction factor from the test load waveform to a driver
launching a wave into a 50 ohm transmission line terminated
at each end by 50 ohms. This must be subtracted from the timing

Thus, the system timing for these parts on a bus would be:

Tco 6.1 ns
Tsetup(data) 3.0 ns
Tjitter 0.25 ns
Tskew 0.4 ns
Tnoise 0.1 ns
Tthreshold 0.05 ns
Tcrosstalk 0.25 ns
driver load correction 0.45 ns

Total 9.70 ns

This leaves approximately 300 ps for signal flight time from
driver to receiver.

These parts are not appropriate for 100 MHz bus operation.



Scott McMorrow
Principal Engineer

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