Re: [SI-LIST] : another stack-up question

Paul Taddonio (taddonio@sky.com)
Fri, 01 May 1998 16:29:52 -0400

D. C. Sessions wrote:
>
> Andrew Phillips wrote:
> >
> > Hi,
> >
> > There was a recent discussion on this list regarding a stack-up proposal
> > for a 10-layer board. Here's another one:
> >
> > signal
> > GND
> > signal
> > signal
> > PWR
> > GND
> > signal
> > signal
> > GND
> > signal
> >
> > I'd be interested in any comments on the merits (or lack of) for this
> > arrangment
>
> Return currents will see a different impedance on PWR vs GND, for one.
> Worse, the returns on 7 & 8 will have to cross layers to get to PWR,
> which should make for (1) much more noise, and (2) assymetrical edges
> at the receiver.
>
> --
> D. C. Sessions
> dc.sessions@tempe.vlsi.com

DC, your answer has left me a little bit confused.
Let me see if I got this right:

The different impedance of GND and PWR is due to many GNDs connected in
parallel (presumably by vias) versus only one PWR plane.

Isn't this alleviated by the PWR plane forming an integrated capacitor
with the adjacent GND plane? (making the PWR plane nearly identical
AC-wise to the GND plane)

Why do you say that return currents have to get back to PWR?

Since they are AC, they flow through the closest AC reference
plane, be it PWR or GND. The only danger occurs if any
signal crosses to another layer which has a different
"closest AC reference plane".

Jumping between 1 and 3, or between 8 and 10 should be OK.

I would like to know more about assymetrical edges, and
how they may arise.

Thanks

-- 
N. Paul Taddonio   phone: 508-250-1920 x245    fax: 508-250-0036

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