Re: [SI-LIST] : =?iso-8859-1?Q?=BB=D8=B8=B4?=: [SI-LIST] : A timing

Scott McMorrow (scottmc@teleport.com)
Tue, 17 Nov 1998 18:57:46 -0800

Here's my hit on the SN74GTL16622 in any design,
based upon data from the TI web site.

Tco 6.1 ns
Tsetup(data) 3.0 ns
Tjitter 0.25 ns
Tskew 0.4 ns

Total 9.75 ns

This total timing path delay does not include the effects
of noise, input threshold variation, board trace crosstalk,
and connector crosstalk. These can be characterized as
follows:

Timing pushout due to noise 1 ps/mV of noise, assuming
a signal edge slew rate of .5 V/ns within the threshold
region. Reasonably one should budget at least 100 ps of
timing pushout for 100 mV of system noise.

Timing pushout due to input threshold variation
1ps/mV * GTL threshold shift.

Crosstalk pushout needs to be simulated at the board
level, and through the connectors. It would be reasonable
to budget150 - 250 ps of pushout due to crosstalk in the
system.

If we use these numbers then we have:

Tco 6.1 ns
Tsetup(data) 3.0 ns
Tjitter 0.25 ns
Tskew 0.4 ns
Tnoise 0.1 ns
Tthreshold 0.05 ns
Tcrosstalk 0.25 ns

Total 10.15 ns

Based upon this, you are correct in saying that it would be
impossible to design a 100 MHz system around these
parts. You are right in saying that there is no margin
for signal flight time. This wouldn't be the first time that
a paper was published about a design which does not
pass worst case scrutiny.

Regards,

Scott

--
___________________________
Scott McMorrow
Principal Engineer
SiQual

mailto:scottmc@teleport.com ___________________________

=C1=F5=CA=F7=B1=F2 wrote:

> My design is not a source synchronous clocking scheme. The clock souce = must > be on one of the daughter boards and be driven to others and of course = the > clock on each daughter board should be synchronous . And the bus is to = be a > share bus , the data both may be driven from the clock daughter board t= o the > others , and may be driven from the others to the clock board . So I th= ink I > have to take the flight time into account. > Is the part not faster enough ? Why the NESA's paper "An Innovative > Distributed Termination Scheme for GTL Backplane Bus Designs" says that > their design use GTL+ (The author mentioned SN74GTL16622 in the referen= ces) > ? >

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