You may be interested to know that the National Center for
Manufacturing Sciences in conjunction with industry is
actively pursuing high eR boards. I am part
of this exercise.
I was particularly interested in the concerns about
flight time and wondered if the group could recommend
some tests (other than the obvious!) that could help set
some boundaries on this technology.
Thank you
Charles Grasso
EMC Engineer
StorageTek
2270 Sth 88th Street
Louisville CO 80027 MS 4262
[email protected]
Tel:(303)673-2908
Fax(303)661-7115
Symposium Website URL: http://www.ball.com/aerospace/ieee_emc.html
>----------
>From: Elya B. Joffe[SMTP:[email protected]]
>Sent: Monday, June 15, 1998 3:58 PM
>To: [email protected]
>Subject: Re: [SI-LIST] : High Permittivity Board Level Decoupling and
>related issues
>
>Dear Members,
>
>
>a) High Permittivity Dielectrics
>
>
>We are considering to use, for RF and ultra-high speed digital circuits,
>very
>high permittivity dielectrics between the PCBs ("Thick Film FODEL").
>
>
>Assume a separation between GND and VCC of 1.6mil, and a dielectric
>constant Epsilon(r) of 5,000.
>
>
>We have calculated that for a sq. Inch of PCB this is "worth" about 700nF of
>decoupling.
>
>
>In this case, would discrete decoupling capacitors actually be necessary,
>would they be of any avail or perhaps even the opposite? Any input on this
>will
>be greatly appreciated.
>
>
>b) Analog Circuit Decoupling
>
>
>Does anyone know any "rule of thumb" for selecting the proper value of
>decoupling capacitors for <underline>analog circuits</underline>? In digital
>circuits - the rise time and
>switching currents of the devices play an important role... What are the
>considerations in Analog circuits???
>
>
>Any reply to either or both questions will be greatly appreciated.
>
>
>Thanks alot,
>
>
> Elya B. Joffe - EMC Engineer
>
><nofill>
>Every success begins with the launching of a dream
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