RE: [SI-LIST] : Decoupling capacitor selection & placemen

Mellitz, Richard (mellitz@xgate.columbiasc.ncr.com)
Fri, 7 Nov 1997 10:04:03 -0500

D.C.

Are you your own straight man? :-) Sorry, ...couldn't resist. Anyhow,
that sounds great! How much C are you going to add and where on the
chips do you plan put it? The I/O ring, core, ...?

.. .Rich Mellitz

>----------
>From: D. C. Sessions[SMTP:dc.sessions@tempe.vlsi.com]
>Sent: Wednesday, October 29, 1997 10:21 AM
>To: si-list@silab.Eng.Sun.COM
>Subject: Re: [SI-LIST] : Decoupling capacitor selection & placemen
>
.... text.....
>The other possibility is that people like me(!)
>will incorporate termination onchip (as the Creator intended it) to
>eliminate stubs and add capacitors onchip (on the RIHGT side of
>bondwire inductance.)
>
>--
>D. C. Sessions
>dc.sessions@tempe.vlsi.com
>
>
>
>----------
>From: D. C. Sessions[SMTP:dc.sessions@tempe.vlsi.com]
>Sent: Wednesday, October 29, 1997 10:09 AM
>To: Andrew Phillips
>Cc: SI-LIST
>Subject: Re: [SI-LIST] : Decoupling capacitor selection & placement
>
>.... text.....
>There's a diminishing-returns function here. After all, many devices
>have a pair of power connections for every four I/Os -- and they have
>32 or 64 I/Os in as little as 5 square cm. When your bypass caps take
>more room than the part, it's time to give up.
>
>--
>D. C. Sessions
>dc.sessions@tempe.vlsi.com
>