Re: component over-stress

George Stevens/UB Networks (George_Stevens@UB.com)
13 Mar 96 10:42:28 EDT

Thanks to all who have responded to this issue. I have included several of the
communications and highlighted (in bold)
what I think may be more pertinent, at this point, to our current situation. To
review, our problem is that a number of these
devices (Srams from Quality Semiconductor) have become damaged in the field and
our only data points are:
-it does not occur on other vendor parts (newer versions)
-out of the 8 Sram array, 5 out of the 8 locations have shown failures (no
failure history to characterize failures at
the pin level)
-one device Failure Analysis by the manufacturer finds an address pin open and
carbon deposits on internal
Vcc/Gnd structures, and a failure characterization of over-stress" by the
application (us).
-over/undershoot measurements on one of the failure locations to reveal no
chip spec violations (during normal
operation), however negative undershoot was observed ranging from -1v to
-2.3v (~-1v for <5ns) constantly.
the manufacturer guarantees latchup immunity to -3v @ 20ns (and advertises
"'excellent latchup immunity")

I believe the comments pertaining to V at input > Vcc is a likely cause. We
will next focus on these types of analysis during system
power up/down and system "hot insertion" modes. Also, it sounds from the
discussions that bus contention would result in a
different failure mode seeing as the Failure Analysis identified a toasted
input pin as well as it being a single driver load..

Questions:
-does latchup condition normally result in a "toasted" Vcc and Gnd structures
on the same IC? Can this effect
be cumulative? The failure mode in the field reports the boards
malfunctioning and requiring manual reset
(I don't believe they were powered down), which worked for several
iterations, then the discovery of the toasted
Srams.

-Are you people interested in hearing more of this saga as it unfolds??? or is
this just nuisance?? I find your
discussions extremely helpful........ Thanks again,

George Stevens
Senior Sustaining Engineer
UB Networks, Andover Ma.

Following is selected communications on this issue:

To: si-list @ silab.Eng.Sun.COM @ SMTP
cc: (bcc: George Stevens)
From: grege @ chensys.com (Greg Edlund) @ SMTP
Date: 03/11/96 03:46:26 PM PST
Subject: Re: component overstress

>I have seen this type of problem many times it's called latchup. This can be
>caused by an overstress at an input, output or I/O pin. The latching mechanism
>is inherant to CMOS devices and is usually triggered by excessive voltage. Most
>designs protect against +/- 7 volts and +/- 100mA static however the pulse
>latchup testing is a better test.
>The place where the latchup mechanism is initiated from does not necessarily
>damage. The damage is usually where the latching currents flow to and from
>namely power and ground metal and associated junction contacts. I put a list
>together of items external and internal to the chip which would cause this to
>happen.
>
> Latch-up trigger mechanisms:
>
> External trigger mechanisms
> Ringing (over shoots) - Poor design.
> System noise
> System power-up and power-down
> (if inputs are generated from a different supply).
> Forward biased junctions at input/output pins
> V at input > Vcc
> V at input < GND
> Worst at elevated temperatures.
>
> Internal Chip trigger mechanisms
> Forward biased junctions on chip - design, layout, device.
> Impact ionization - design
> C dV/dT current - design, layout, external noise
> Punchthrough current - device, process
> Field inversion - process
> Junction leakage (light) - process
> Defects (fab and reliability failures)
>
>Hope this is helpful.
>
>regards
>
>AC
>
> --------------------------------------------------------------------------
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>| Disclaimer: My opinions may not reflect those of my kind employers. |
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>
>
>

My two bits:

I believe latch-up is defined as a positive feedback
mechanism which has its origins in a parasitic SCR
(silicon controlled rectifier), which is a sandwich
of p-n junctions arranged in this order: p-n-p-n.
I'm not sure about how you get the positive feedback...

If you had a bus contention problem, I think you'd
expect to see a power pad toasted on one chip and a
ground pad toasted on another chip. You can also have
problems with a 5 V device and a 3.3 V device trying to
drive the same line high. Sounds like a power and a
ground pad toasted on the same chip would lead you more
toward the latch-up hypothesis.

--
Greg Edlund                o---/\/\/\---+-----+---o
Circuits and Modeling                   |     |
Chen Systems Corp.                      |      )
1414 W. Hamilton Ave.                 -----    )
Eau Claire, WI 54701                  -----    )
voice (715) 833-7067                    |      )
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email grege@chensys.com    o------------+-----+---o

To: si-list @ silab.Eng.Sun.COM @ SMTP cc: (bcc: George Stevens) From: artc @ lobsang.sps.mot.com (Arthur Collard) @ SMTP Date: 03/11/96 04:28:17 PM PST Subject: Re: component overstress

Greg is correct about the power/ground pads toasted being a latchup mechanism. The parasitic SCR is formed at the pin circuitry by the CMOS layout. There are design rules to protect from this occuring however the immunity vs. layout area tradeoff is of concern also. The key here is that the pin is the entry point where the current flows into the SCR to trigger the latch. This will occur when the product of the parasitic NPN and PNP beta (open loop gain) is > or = 1. Latch-up begins at one location and spreads drastically to several other locations across die. Once the SCR is triggered the currents flow directly from Power to Ground and cannot be stopped unless the chip is powered down. By this time the chip has been overstressed and most likely damaged. The damage occurs when the metal/silicon contact resistance drops (due to aloying) to the point that the internal power metal evaporates (opens). The SCR is a current triggered device so the assumption that several drivers on on pin maybe correct but voltage overshoot must occur to foward bias a pn junction.

Hope this helps

Regards

AC

-------------------------------------------------------------------------- | M O T O R O L A - Advanced Microcontroller Division (AMCU) | | ------------------------------------------------------------------------ | | Art Collard Modular Circuit Design email: artc@amcu-tx.sps.mot.com| | ------------------------------------------------------------------------ | | Mail Drop: OE320 | | Motorola - Advanced Microcontroller Division | | 6501 William Cannon Drive West, Austin, Texas 78735-8598 | | Tel: (512)891-8651 Fax: (512)891-3348 Pager: (512)933-7333 pgr# 89-8651| | Disclaimer: My opinions may not reflect those of my kind employers. | --------------------------------------------------------------------------

To: George_Stevens @ UB.com @ SMTP cc: andresen @ asic.sc.ti.com @ SMTP (bcc: George Stevens) From: andresen @ asic.sc.ti.com (Ben Andresen) @ SMTP Date: 03/11/96 05:28:16 PM PST Subject: Re: component overstress

George, any chance the inputs of the SRAMs could be driven high before their Vdd is applied. This would result in high input current flow as the Vdd bus would be driven through the SRAM input clamp diodes. A second thought is there may be occassional power supply/signal spikes causing EOS, but they are infrequent enough that you don't see them in your evaluation. Contention might burn out the output drivers if it were severe enough, but I don't se it damaging the input.

Ben