thanks to all that wrote and asked me about the ASIC "Blip" problem. Here is
what I found:
The ASIC has 4 power pins, it would appear that the blip only occurred on the
outputs "associated" with a single power pin. The decoupling cap on this pin
is about 1/2" away from the ASIC, the other decoupling caps are almost on the
pins. To make things worse, the via to the power plane feeds the trace going
to the cap and not the ASIC.
I noticed that the power pin had a very fast ( about 2 ns ) -ve pulse
occasionally the larger -ve pulses appear to be sufficient to cause the
outputs associated with that power pin to move - I believe this was the cause
of my "blip". An ad-hoc cap on the power pin seems to have stopped it.
When I did my measurements, I recorded that the ASIC outputs changed state
between 1 and 2 ns, this is way too fast for my needs, is there any LOW COST
way to selectively slow down a transition by an order of magnitude?