# Re: Power/ground connections/bypassing on ICs

Howard Johnson ([email protected])
Mon, 5 May 1997 14:31:32 -0700 (PDT)

There is a reasonable discussion of
how to design a bypass array in
Chapter 8 of "High Speed Digital Design",
by (this author) Howard W. Johnson and
MArtin Graham, Prentice Hall, 1993,
ISBN 0-13-395724-1.

**Also, I would like to echo the comments
of many others.
with bypass capacitors *decreases* their
effectiveness
(2) Adding traces in series with the Vcc/Gnd
pins of an IC does *not* help prevent noise
from the IC from reaching the Vcc/Gnd

For high-speed digital designs, and also
for mixed-signal designs,
I place vias as close to the capacitor pads
as possible, leading directly to the Vcc/Gnd planes.
I also place vias as close to the IC power and
ground pins as possible, leading directly to the
Vcc/Gnd planes.

Let's look at the example that started this discussion:

+----------+
###| |###
| |
###| |###
vias | |
X=====###========###| |###
| | | |
X=====###========###| |###
bypass | |
capacitor ###| |###
+----------+
I.C.

Some engineers believe
that putting traces in series with the IC power
and/or ground pins will reduce the amount of
noise that reaches the Vcc/Gnd planes.
It doesn't.
The reason why has to do with the relative
impedances involved, and the problems with
ground bounce. Here's a general explanation:

First, consider the chip as a source of noise.
The output impedance of the chip (the effective
driving point impedance of the chip's Vcc and Gnd
pins) is always GREATER
than the Vcc/Gnd impedance of a properly designed
board (if it's not, then you have a whopping
huge amount of Vcc/Gnd noise). This ratio
is what controls Vcc/Gnd noise.

Whenever your noise source has a higher
impedance than the load, the noise source
acts like a "current source". In effect,
it pumps a fixed amount of current onto
the Vcc/Gnd system.

Putting an impedance, like a little
circuit board trace, in series with a current
source is futile. It doesn't affect
the amount of current delivered to the Vcc/Gnd
planes, and therefore doesn't affect the Vcc/Gnd
noise.

In order to substantially affect the amount of
current going into the Vcc/Gnd planes you would
need to insert in series with the chips Vcc/Gnd
pins a trace with an impedance *as large*,
or larger than the driving point impedance of the chip.
But, that's impossible, becuase an impedance that
large would create riduculous amounts of ground
bounce (or Vcc bounce) in the chip.

Now, let's look at the problem in a little more
detail.

Imagine that the chip below has eight outputs, and they have
all been set to LO for quite some time. At time
Tzero, let them all switch HIGH.

If the outputs are heavily loaded, the chip must now source a
huge pulse of current. This current flows in to the chip
through its VCC pin, and out to the loads through its
eight output pins.

From the Vcc plane, this pulse of current must flow along
path (A) to the chip. As the current passes through
path (A), we develop a voltage across the inductance
of path (A). If this voltage is small, we haven't modified
the amount of current flowing from the power system.
If this voltage is large, we have so much VCC noise
at the chip that it may not function. Catch-22. You
can't win.

+----------+
###| |###
| |
###| |###
vias (A)---> | |
Vcc plane X=====###========###| VCC |###
| | | |
Gnd plane X=====###========###| GND |###
| |
bypass ###| |###
capacitor +----------+
I.C.

If you wish to prevent a noise chip from interfering
with the reset of your system, here is a better approach:

The Vcc plane (A) connects through inductor (B) to
a bypass capacitor (C). Tbe bypass capacitor has a
short-wide connection (aspect ratio 1:1 or less) to
the VCC pin (D).

The Gnd plane connects through a via directly
to the bypass capacitor (E).

The Gnd plane connects through a via directly
to the chip GND pin (F).

+----------+
###| |###
| |
###| |###
(A) (B) (C) | (D) |
Vcc plane X==== L ====###=###| VCC |###
| | | |
Gnd plane X=### ###|=X GND |###
(E) | (F) |
###| |###
+----------+
I.C.

This arrangement reduces noise flow in both directions, from
the system into the chip, and from the chip into the system.

Ground bounce is conquered because I have provided a low
impedance via from the GND pin (F) to the Ground plane.

Vcc bounce is conquered because I have provided a low
impedance path from the VCC pin (D), through the
bypass capacitor, to its gound via (E).

Best regards,
Dr. Howard Johnson

At 12:05 PM 4/28/97 -0600, you wrote:
>I can't remain quiet on this issue any longer.
>
>We all know about minimizing and reducing, etc. But does anyone out there
>actually DESIGN their bypassing networks? I sure don't know how to do it!
>
>If I did, perhaps I could design a bypass network that would serve my needs
>AND the needs of the assembly/manufacturing folks. A few years back, at a
>SPICE class in San Jose, I heard a fellow from IBM state that he designed his
>bypassing networks in the frequency domain. Anyone else doing this?
>I've tried, but without satisfactory results. Any suggestions on scaling
>the problem? Any ideas on how to model the timing jitter between parts
>that are simultaneously switching with ~2ns edges? Are there any bypass
network
>designers out there? I'm sure I (at least) could use some real design help on
>this one. No opinions, intuitions or hand-waving please. I have plenty of my
>own and they are probably more conservative than need be.
>
>Gary P.
>---
> Gary D. Peterson
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_________________________________________________
Dr. Howard Johnson, Signal Consulting, Inc.
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