Your trying to analyze the circuit statically and it won't work. This is
not a resistive network. As poined out there is a wide frequency range
where the capacitive effects dominate. Xc the capacitive reactance will
will change the computed reflection coef. over frequency. As a first
approximation you can guess that the reflection coef. is infinite or
very large. The input capacitance of a cmos even with parasitic and all
is still in the 10's of pf range or smaller. This makes the reactance
quite large even at high frequencies like 100Mhz.
What you really need is SI tools that can easily model the interconnects
and the IC. This gives you the dynamic answer to your question. There
are plenty of good tools out there, some are cheap, some very expensive.
Check out one of these that fits your budget and needs.
Best Regards,
-- Fred Balistreri fred@apsimtech.com**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****