[SI-LIST] : Intelligent Placement of Decoupling Capacitors

Raymond Chen (chen@sigrity.com)
Fri, 13 Feb 1998 04:26:16 +0000 (GMT)

Last week, I read with great interest in the message posted on SI-list by
Lawrence, as well as the comments of Frank Yuan. The problem raised in
Lawrence's message is actually almost identical to one of our demo
examples of our software tool - SPEED97. Lawrence is quite right that "a
capacitor might be needed at that via site even through there are no
components nearby." The current in that via is really the main source
that generates the fluctuation of voltage between the power and the ground
planes. Therefore, the most effective place to put the capacitor is that
via site. In practice, one should also put capacitors elsewhere on the
board to ensure steady power and ground supply throughout the board and to
prevent resonance inside the board. To help understand the physics of
what is happening, I used SPEED97 and made a full-wave animation of
electromagnetic field propagation between the power and the ground planes.
Good location for placing the decoupling capacitor is also demonstrated
through the full-wave animation. I placed these animations together with
some discussions on our web site (http://www.sigrity.com) for interested
SI-listers.

Raymond Chen
SIGRITY. INC.

> > Lawrence Butcher <lbutcher@parc.Eng.Sun.COM> wrote:
> >
> > Imagine that I build a 4 layer board. Imagine that there were two
> > chips on it, labeled U1 and U2. Imagine that I route the board
> > strictly manhatten style. All horizontal wires are on top above the
> > ground plane, and all vertical wires are on the bottom below the power
> > plane.
> > _______________
> > | |
> > | U1 ------* |
> > | | |
> > | | |
> > | | |
> > | U2 |
> > |_______________|
> >
> > Normally, I would put bypass caps under U1 and bypass caps under U2.
> > I would cosy them up so that there was minimum distance between the
> > caps and the power supply pins on the chip.
> >
> > Consider the image currents running on the power and ground planes.
> > An image current will sit directly under each wire. But that current
> > will have a hard time following the wire through the via, because it
> > would have to hop from the ground plane to the power plane.
> >
> > It seems clear that a capacitor might be needed at that via site to
> > give the current in one plane a chance to hop to the other. Even
> > though there are no components nearby.
> >
> > Intuition rarely substitutes for calculation. Question: Is this true?
> > How much capacitance? How does that vary if there are 40 wires instead
> > of 1? How does the number change with frequency?
> >

> Dr. Frank Yuan <fyuan@qdt.com> replied:
>
> Lawrence,
>
> First, the image current on power or ground plane sit directly under the
> trace will run in opposite direction as the trace current. Therefore
when
> U1 send trace current out, the image return current on the plane flow
> right back towards U1, and go through bypass caps under U1 to power
plane.
> This is why bypass caps should be, as you said, very close to
power/ground
> pins on the chip. Seems to me no capacitors are needed at the via site
or all
> over the board just for return path. However, de-caps may be need evenly
> over the board to supress power/ground noises (SSN) on the planes.
>
> Again accurate calculation helps a lot in answer those questions. An
> simulation tool call AC_GRADE from Viewlogic (Formerly Quad Design)
> does just that in analyze power and ground planes and the effects of
> decoupling capacitors.
>