GND/V33 pair and V5/GND pair would act as an integrated decoupling capacitor,
the value of which would depend on the dielectric thickness between the
planes. Thinner the better. If too many drivers are not switching, and signal
required is small, discreet decap at the via site may not be required at all.
switching is an issue, and don't want to use discrete decaps, you might want
to consider reducing the thickness of the layer between GND and V33 and also
for other pair.
I agree with Frank that split plane would not be a very good idea and you may
have to do lot of analysis and modeling to understand all the possible current
and SI issues and if the V/H signals are not laid out correctly you may end
longer current paths on the GND/PWR planes giving rise to more switching
Frank Yuan wrote:
> First, the image current on power or ground plane sit directly under the
> trace will run in opposite direction as the trace current. Therefore
> U1 send trace current out, the image return current on the plane flow
> back towards U1, and go through bypass caps under U1 to power plane.
> is why bypass caps should be, as you said, very close to power/ground
> on the chip. Seems to me no capacitors are needed at the vis site or all
> over the board just for return path. However, de-caps may be need evenly
> over the board to supress power/ground noises (SSN) on the planes.
> Again accurate calculation helps a lot in answer those questions. An
> tool call AC_GRADE from Viewlogic (Formerly Quad Design) does just that
> analyze power and ground planes and the effects of decoupling
> For your 8-layer board, I would like a stuckup like
> 1 Horizontal
> 2 V33 Plane
> 3 GND Plane
> 4 Vertical
> 5 Horizontal
> 6 GND Plane
> 7 5V Plane
> 8 Vertical
> This way, you can connect the two GND planes througn internal vias, and
> bypass on either 3.3V or 5V will be effective for both GND planes.
> I do not agree the use of split 3.3V and 5V plane. This is a very
> practice unless it is absolutely necessary. A trace cross over a split
> is very likely to have serious SI problem. Also, if possible, one should
> always put power and GND planes together for increased inter plane
> and better shielding.
> Frank Yuan, Ph.D.
> Viewlogic Systems Group
> Camarillo, CA
> Lawrence Butcher wrote:
> > Imagine that I build a 4 layer board. Imagine that there were two chips on
> > it, labeled U1 and U2. Imagine that I route the board strictly manhatten
> > style. All horizontal wires are on top above the ground plane, and all
> > vertical wires are on the bottom below the power plane.
> > _______________
> > | |
> > | U1 ------* |
> > | | |
> > | | |
> > | | |
> > | U2 |
> > |_______________|
> > Normally, I would put bypass caps under U1 and bypass caps under U2.
> > I would cosy them up so that there was minimum distance between the
> > caps and the power supply pins on the chip.
> > Consider the image currents running on the power and ground planes.
> > An image current will sit directly under each wire. But that current
> > will have a hard time following the wire through the via, because it
> > would have to hop from the ground plane to the power plane.
> > It seems clear that a capacitor might be needed at that via site to
> > give the current in one plane a chance to hop to the other. Even
> > though there are no components nearby.
> > Intuition rarely substitutes for calculation. Question: Is this true?
> > How much capacitance? How does that vary if there are 40 wires instead
> > of 1? How does the number change with frequency?
> > The above illustrates a real problem. I am building an 8-layer board,
> > with a tentative stackup of:
> > 1 Horizontal
> > 2 GND Plane
> > 3 V33 Plane
> > 4 Vertical
> > 5 Horizontal
> > 6 V5 Plane
> > 7 GND Plane
> > 8 Vertical
> > My component placement places all of the 3 volt components above the
> > midline of the board, and all of the 5 volt components below the midline.
> > Therefore, there are NO bypass caps from the 5V plane to ground in the
> > top half of the board, and NO bypass caps from the 3.3V plane to ground
> > in the bottom half of the board.
> > A trace running horizontally on layer 5 in the top half of the board
> > will have an image current running on the V5 plane, and that current
> > has no way to get to the ground plane at a via site. Same for traces
> > running on layer 4 in the botton half of the board.
> > I want to add about 1 cap per square inch (about 50 more bypass caps).
> > Half will be between V5 and ground in the top half of the board, and half
> > will between V33 and ground in the bottom half of the board.
> > These components are there only to deal with my paranoia about image
> > currents. They would be placed even though there are already tons of
> > bypass caps in the same area, but exclusively to only one power plane.
> > My coworkers have doubts. They especially don't like 50 more caps when
> > there are no nearby chips connected to the power planes I am concerned with.
> > Most of my signals are changing at 100 MHz, but there is a bunch of 33 MHz
> > activity running around. (Fast, for me).
> > Is this a non-existent problem, or a real one? Comments?
> > Lawrence