> If you have split lines, normally the termination values are 2x65 Ohm
> each end.
That may be the usual RF way; but for digital signals, you would lose
half your signal. AGP clocks should be source-terminated only.
> It seems that you have 2 signals between the gnd and Vcc, this is not
> good for
> high speed circuits > 100MHz, I should think it will still work for
> Mhz. We normally
> recommend to have gnd and Vcc coupled together, S,S,GND,VCC,S,S
> 1,2, 3 , 4 , 5 ,
> The most critical clocks and lines are routed in 2 and 5. We have
> with signal integrity simulation that show the integrity will degrade
> you put the signals
> in between the Vcc and Gnd.
Can you suggest an explanation for why you had a problem when you used
stripline rather than microstrip? Generally, stripline is preferred,
and it is very common to put signal layers between Vcc and Gnd. Of
course you want to keep them orthogonal to minimize crosstalk, and use
good HF bypassing everywhere between the planes.
Diaco Davari wrote:
> According to the Emission data gathered with AGP video card in place,
> are still marginally above limit. We have already tried different
> of damping resistor at source and load side. Also, tried small value
> Caps on both ends to match the impedance of the line with source and
> load, but no cleaner signal or better emission performance observed.
Then are you sure the clock is the source of the emissions? Could it be
one of the chips itself? Or power? Or this or another bus (not just
the clock)? Could it be coupled from clock into another line that goes
to a surface layer or connector?
> Also, enabling the Spread Spectrum on clock generator has no effect on
> the 66 MHz clock that comes out of the PLL section of the Intel chip.
That's because the PLL filters out the spread spectrum modulation.
(What this does to your clock skew, that's another question.)
If your instrumentation is narrow band so that you could see a reduction
in peak amplitude with spread spectrum clocking enabled, and if so
enabling it has no effect on emissions, then this tends to indicate that
your emissions are NOT coming from the clocks before the PLL.
> The cerpentined feed back segment Placed interlayer next to
> GND plane and placed right under the Intel chip.
I tend to think that long double-backs are better than short squiggles,
but this isn't because of EMC.
> The clock line that
> feeds AGP connector only switches once from inter layer plane A to B.
Where the trace (any trace) switches between those layers, make sure
there's good HF decoupling near the via. The return current for that
clock must also transition between GND and VCC planes. Give it a low
inductance path, or it will have to spread out to find a path.