[SI-LIST] : CMOS off-chip driver design

Michael Gutzmann (micha@c-lab.de)
Thu, 26 Feb 1998 10:45:12 +0100 (MET)

Hi,

my question concerns the CMOS off-chip driver design.

There is a plenty of design techniques to control the drivers output
current or output edge slew rate in order to e.g. reduce SSN.

Is there any kind of CMOS off-chip driver that really use their output
voltage/current as controlling parameter in a FEEDBACK LOOP to drive
the input of the final stage of the driver?

IF YES,
I hope there's any chance that someone provides me with one
example of such a type of output driver for my SSN modeling work
as part of my PhD thesis (preferrably as HSPICE model).

I am not interested in getting a look into latest technology
informations but I need a real design of such type of output driver
(if existing) to investigate differences of the transient behavior of
drivers with and without feedback loop in principle.

So I could live with an example of an earlier technology.

All feedback are welcome.
Best Regards

Michael