[SI-LIST] : Re: [SI-LIST]: SSO noise: Through current vs. Discharge current]

Michael Gutzmann (micha@c-lab.de)
Mon, 29 Sep 1997 10:19:39 +0200

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Hello John,
(Sorry I haven't read your references)

My thoughts regarding to your question are the following:

In real-life buffers (in CMOS design) the output stage that
mostly contributes to the SSN of the buffer is in general
a simple CMOS inverter.
They are designed as usual such that there is an input voltage
range from V_tn to (Vdd-V_tp) when both transistors are ON.

Nevertheless the (dis-)charge current will be the dominating
part of the current flowing through the effective inductance
L_GND or L_VCC, respectively.

The reason is the relation between input and output signal edge
of the inverter. The maximum possible through current of a considered
inverter occurs at the time when V_in=V_out WITHOUT an external
load. For a symmetrical inverter V_in=V_out will be at VDD/2
(parasitic transistor capacitances neglected).

Lets have a LOW-TO-HIGH transition of the input voltage WITH an
external load:

If an external load is connected to the output,
the falling output signal edge will be
of course very much slower than in case of an unloaded inverter.
So the threshold when V_in=V_out will move towards VDD and therefore
the maximum through current of the PMOS will be much smaller.
If you imagine the extrem case of a very large capacitive load, then
the input signal edge has been completed when the output voltage
is still nearly at VDD, you will nearly have no through current at all.

Influence of CL and Z0 on SSN:

CL:
As described by Senthinathan et.al the turning-on transistor behaves
like a (nonideal) current source till this transistor leaves the
saturation region. At that time the maximum drain current and
in approximation also the maximum di/dt will occur.
In case CL is above a critical value, the output voltage changes very
slowly (with respect to the input signal edge).
So the maximum di/dt is determined by the end of the input signal edge
and INDEPENDENT of CL.
In case CL is below this critical value, the output voltage changes
faster and the turning-on FET leaves the saturation before the
input edge is completed. Then the maximum di/dt will be smaller
and DEPENDS on CL.

Z0:
The physical background is the same as mentioned for CL. So you will
have a Z0_min somewhere (mostly a pretty small value below
typical values of Z0 for PCBs) when the SSN will have its maximum.
Increasing
Z0 above Z0_min will decrease the SSN, but I guess not as strong as
(IZ/ISC)*SSN_max suggests.

Best regards,

Michael

John V Fitzpatrick wrote:

> Hello,
>
> Several weeks ago I asked a question to the list concerning
> simultaneous switching noise (SSN). I received many useful
> answers. Most pointed me towards Senthinathan and Prince,
> which I have ordered, but not yet received.
>
> One issue that concerned me was the influence of load
> capacitance on the SSN. The answer, it seems, depends on
> the design of the output buffer:
>
> 1) If the P and N transistors are momentarily ON,
> then the "through" current dominates, which means that
> the maximum noise amplitude is independent of the load.
> This is because the di/dt of the through current is greater
> than the di/dt of any (dis-)charge current.
>
> 2) If the output buffer is designed so that the P and N
> buffers are never both ON, then the SSN source
> is predominately the (dis)charge current. SSN increases
> with Cload up to a certain value of Cload, then plateaus
> off (Vmax).
> If the Cload is replaced by a transmission line, then
> then a simple rule is that the SSN is (Iz/Isc)*Vmax,
> where Isc is the short-circuit output current and Iz is the
> output current for a resistance equal to the impedance of
> the line.
>
> This interpretation prompts the following question:
>
> Are real-life buffers designed such that the P and N
> transistors are never ON simultaneously?
>
> Comments?
>
> Salutations,
> John
>
> --
> John Fitzpatrick <John.Fitzpatrick@ln.cit.alcatel.fr>
> Alcatel Telecom, 4 rue de Broglie, 22304 Lannion, France
> Tel: +33(0)2.96.04.79.33 Fax: +33(0)2.96.04.85.09

-----
Michael Gutzmann
C-LAB / Analog System Engineering
Fuerstenallee 11, 33102 Paderborn
e-mail: micha@c-lab.de

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Subject: Re: [SI-LIST]: SSO noise: Through current vs. Discharge current
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Hello John,
(Sorry I haven't read your references)

At first the answer to your question:

In real-life buffers (in CMOS design) the output stage that
mostly contributes to the SSN of the buffer is in general
a simple CMOS inverter.
They are designed as usual such that there is an input voltage
range from V_tn to (Vdd-V_tp) when both transistors are ON.

Nevertheless the (dis-)charge current will be the dominating
part of the current flowing through the effective inductance
L_GND or L_VCC, respectively.

The reason is the relation between input and output signal edge
of the inverter. The maximum possible through current of a considered
inverter occurs at the time when V_in=V_out WITHOUT an external
load. For a symmetrical inverter V_in=V_out will be at VDD/2
(parasitic transistor capacitances neglected).

Lets have a LOW-TO-HIGH transition of the input voltage WITH an
external load:

If an external load is connected to the output,
the falling output signal edge will be
of course very much slower than in case of an unloaded inverter.
So the threshold when V_in=V_out will move towards VDD and therefore
the maximum through current of the PMOS will be much smaller.
If you imagine the extrem case of a very large capacitive load, then
the input signal edge has been completed when the output voltage
is still nearly at VDD, you will nearly have no through current at all.

Finally to the influence of CL on the SSN:

As described by Senthinathan et.al the turning-on transistor behaves
like a (nonideal) current source till this transistor leaves the
saturation region. At that time the maximum drain current and
in approximation also the maximum di/dt will occur.
In case CL is above a critical value, the output voltage changes very
slowly (with respect to the input signal edge).
So the maximum di/dt is determined by the end of the input signal edge
and INDEPENDENT of CL.
In case CL is below this critical value, the output voltage changes
faster and the turning-on FET leaves the saturation before the
input edge is completed. Then the maximum di/dt will be smaller
and DEPENDS on CL.

Best regards,

Michael

John V Fitzpatrick wrote:

> Hello,
>
> Several weeks ago I asked a question to the list concerning
> simultaneous switching noise (SSN). I received many useful
> answers. Most pointed me towards Senthinathan and Prince,
> which I have ordered, but not yet received.
>
> One issue that concerned me was the influence of load
> capacitance on the SSN. The answer, it seems, depends on
> the design of the output buffer:
>
> 1) If the P and N transistors are momentarily ON,
> then the "through" current dominates, which means that
> the maximum noise amplitude is independent of the load.
> This is because the di/dt of the through current is greater
> than the di/dt of any (dis-)charge current.
>
> 2) If the output buffer is designed so that the P and N
> buffers are never both ON, then the SSN source
> is predominately the (dis)charge current. SSN increases
> with Cload up to a certain value of Cload, then plateaus
> off (Vmax).
> If the Cload is replaced by a transmission line, then
> then a simple rule is that the SSN is (Iz/Isc)*Vmax,
> where Isc is the short-circuit output current and Iz is the
> output current for a resistance equal to the impedance of
> the line.
>
> This interpretation prompts the following question:
>
> Are real-life buffers designed such that the P and N
> transistors are never ON simultaneously?
>
> Comments?
>
> Salutations,
> John
>
> --
> John Fitzpatrick <John.Fitzpatrick@ln.cit.alcatel.fr>
> Alcatel Telecom, 4 rue de Broglie, 22304 Lannion, France
> Tel: +33(0)2.96.04.79.33 Fax: +33(0)2.96.04.85.09

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