Re: vias in ECL @ >1Ghz

Tom Giovannini (tjg@appsig.com)
Wed, 2 Apr 97 13:04:43 PST

Hello,

I read an email about 1GHz ECL vs. vias. I accidentally erased the
original email, so I don't have a return address. So, I'm sending
this out to the general email list in hopes that it will get to the
originator of the question....

In general, vias in GHz nets should be avoided. However, this forces
traces to run on microstrip layers that are not optimum for noise and
dispersion.

An alternative is to have only two vias in the net: one via
lumped (with respect to the rise time of the signal) with the driver
chip pad and one via lumped with the load chip pad . Each via can usually
be part of the chip pad breakout (assuming a very short breakout trace).
This lumps the via parasitics with the driver/load pin/pad parasitics, and
this usually has the behavior of extra driver/load parasitic capacitance.
The mainline trace between the vias should then be routed on the same
stripline layer with no vias along its path. For differential nets, the
two nets should have exactly the same pad/via/trace topology and should be
matched in length.

Lumping the vias at the driver and load ends of the net then leads to
a predictable net response. An example for this is outlined for a high-rate
ECL clock network in a paper I wrote back in 1992, "Simple Approach Optimizes
ECL Clock Networks," Microwaves & RF, October, 1992. The outlined method
provides net length constraints for optimimum signal/timing quality at the
load chip for a lumped driver/load net.

Let me know is this helps.

Tom Giovannini
tjg@appsig.com