RE: [SI-LIST] : 66 MHz AGP Clock Signal

Diaco Davari (
Wed, 15 Apr 98 11:11:58 -0800

Hello Andrew,

Thanks for all your inputs. I also think Interlayer is the best technique
to use on clocks.

You wrote:

Then are you sure the clock is the source of the emissions? Could it be
one of the chips itself? Or power? Or this or another bus (not just
the clock)? Could it be coupled from clock into another line that goes
to a surface layer or connector?
That's because the PLL filters out the spread spectrum modulation.
(What this does to your clock skew, that's another question.)
If your instrumentation is narrow band so that you could see a reduction
in peak amplitude with spread spectrum clocking enabled, and if so
enabling it has no effect on emissions, then this tends to indicate that
your emissions are NOT coming from the clocks before the PLL.
I tend to think that long double-backs are better than short squiggles,
but this isn't because of EMC.
Where the trace (any trace) switches between those layers, make sure
there's good HF decoupling near the via. The return current for that
clock must also transition between GND and VCC planes. Give it a low
inductance path, or it will have to spread out to find a path.

The only place that produces 66 MHz is the Intel PLL chip, by using the
most sensitive close loop probe and following the path of the highest
value of emissions related to harmonics of 66 MHz (Specifically 330 & 462
MHz) partially proves that the infected area is where this 66 MHz clock
runs toward AGP port. But, I am not saying that the chip is totally

Also, found that the level of emission is much higher at the load side
near the first pin counts of the AGP port where this clock pin will
surface the top layer and I can not detect the same level of emission all
around the AGP connector. We can not analyze what happens to interlayer

On our last product that was based on a 4 layer stackup, we had a good
margin related to the 66 MHz AGP harmonics. 66 MHz clock trace was 2 inch
shorter and placed on top/bottom of the PCB.

When looked at 300 MHz on the spectrum analyzer (under lower SPAN) we can
see the composite of Spread Spectrum (100 MHz harmonics at 300) & Narrow
Band (66 MHz harmonics at 330). The peak level of the Narrow Band is at
least 10 dB higher than Spread Spectrum harmonics and that is why we fail
at 330 and not 300 MHz.

But, you have mentioned a good point, you said "Where the trace switches
between those layers, make sure there is a good HF decoupling near the
via". I am going to look into this and see what I can do about it.

Please let me know if you have any other watch out points.

Appreciate your continued response,