Re: [SI-LIST] : PCB parameters

fabrizio zanella (fabrizio=zanella%eng%emchop1@fishbowl02.lss.emc.com)
Fri, 19 Sep 97 10:38:06 -0400

I wonder what board shop that was? Chris, I saw your badge at the IBIS
meeting last night, Mark was there, and lots of DEC engineers. It wasn't a
bad meeting. Ed Sayre made a statement that no one was there from
networking companies because you guys are too busy. So how's everything?
We're expecting our 3rd child in January (are we crazy? maybe). Are you
still involved in sports? I just finished playing soccer for an EMC team,
and now I'm coaching my son's team in Milford, MA.
Take care, Fabrizio.
-------------
Original Text
From: Chris_Heard/US/3Com%3COM@SMTP1.isd.3com.com, on 9/19/97 8:06 AM:
To: smtp@Eng@EMCHOP1["Weber Chuang" <WeberChuang@via.com.tw>]
Cc: smtp@Eng@EMCHOP1["'Joachim Mueller'" <jmueller@ca.newbridge.com>],
smtp@Eng@EMCHOP1["John Lin - TAO" <LinJohn@mail.dec.com>],
smtp@Eng@EMCHOP1["si-list" <si-list@silab.Eng.Sun.COM>]

FROM too long. Original FROM is
"Chris Heard/US/3Com" <Chris_Heard/US/3Com%3COM@SMTP1.isd.3com.com>

---------------------- Original Message Follows ----------------------
The PCB vendor must gather data that correlates the results of 2D
sectioning
and TDR results with a numeric 2D field solver. The reason is that effects
such as surface roughness, 0.3mil high "teeth" on the core material side of
the
trace, and crossed pattern bundles of glass weave are typically not
included in
most 2D solvers.

I know of one vendor where this worked very well until purchasing decided
to
buy core material from a different vendor, then the empirical plus
analytical
models became less accurate.

Chris

----- Previous Message ----------------------------------------------------

To: jmueller @ ca.newbridge.com @ SMTP1
LinJohn @ mail.dec.com @ SMTP1
cc: si-list @ silab.Eng.Sun.COM @ SMTP1
From: WeberChuang @ via.com.tw (Weber Chuang) @ SMTP1
Date: Friday September 19, 1997 10:18 AM
Subject: [SI-LIST] :
=3D?Big5?B?pl7C0CA6IFtTSS1MSVNUXSA6IHN0YWNrdXAgaW1wZWRhbmNlLg=3D=3D?=3D
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Yes, I do totally agree, and that's what we are doing right now in my
corp.. However, simulation should be used to help the speeding up of
design cycle, so we are trying to make a correlation between
simulations and empirical data base which we think might help us in the
future development. So is there anyone has ever tried such approach?
If Yes, is there any particular step that needs to be taken care of? Can
you talk about this?

regards
weber
SI Eng.
VIA Tech.

> -----=A1k}lZl=D1s-----
> _H=D1s=AC=A6: Joachim Mueller [SMTP:jmueller@ca.newbridge.com]
> ZG_e=AB+Z=ED: 1997=AA~9=F1=A619=F1=BC =F1W=F1+ 12:35
> =AA=BC=D1s=AC=A6: John Lin - TAO
> _F=D1+: si-list@silab.Eng.Sun.COM
> =D1D=AA=AB: Re: [SI-LIST] : stackup impedance.
>
> Hi,
> I am a fan of numerical field solver too. I have no doubt that the
> results are accurate. But the problem is that the PCB manufacturing
> process is not as accurate as the field solver is. There are parasitic
> parameters involved which are usually not considered in simulation
> models.
>
> If the stackup has two or more adjacent signal layers, the coupling
> between
> the traces on different layers is hard to model but will influence the
>
> characteristic impedance. It is certainly not the case that you want a
> strong
> coupling between all four signal layers (second stack up) by routing
> them on
> top of each user.
>
> >From all that, we found that the most accurate is to get an empirical
> data base (measurements) from the board shop.
>
> Joachim
>
> --
> +---------------------------------------------------------------------
> +
> | voice: +1 613 591 3600 | Joachim Mueller, EMC-Approvals
> |
> | fax : +1 613 599 3654 | 600 March Rd. P.O. Box 13600
> |
> | e-mail: jmueller@newbridge.com | Kanata, Ontario, (CA) K2K 2E6
> |
> +---------------------------------------------------------------------
> +
> | Newbridge Networks Corporation
> |
> |
> |
> | __o
> |
> | _`\<,_
> |
> | (_)/ (_)
> |
> | ~~~~~~~~~~
> |
> +---------------------------------------------------------------------
> +
>
>
> >
> > Hi,
> > Does anybody have idea about how to calculate the impedance of
> > stackup with following structures.
> >
> > S-S-G-P-S-S ( 6 layers).
> >
> > and
> >
> > G-S-S-S-S-P (6 layers).
> >
> > I checked books and tried to find equations to calculate impedance.
> > However, I cannot find any.
> >
> >
> > Best Regards,
> >
> > JOHNLIN
> > CAE Engineer of EDA Department
> > Digital Equipment Corp. Taiwan Branch
> > Email: Linjohn@mail.dec.com
> > TEL: 1-886-3-3900000 ext. 2565
> >
> >
> >
>
>
>
>