I'm working on designing individual pcb structures (with end launched SMA
connectors) as well as combined structures that include circuits to launch
2.5 Gbps serial channels technology to develop a technology base.
What I'm concerned about is trying to develop enough test structures so that
I can determine which combination of structures will allow me to use these
circuits in real multi-layer pcb's (if indeed they can)...All eval boards
and recommendations from venders are advocating
1) Stay away from via's
2) Use traces that are as wide as the pand patterns for discretes
and the circuit packages
3) etc., etc.
Realizing that indeed this requires a much more sophisticated approach to
layout then circuits below 1 GHz, I'm inclined ask
1) What is it about a via that is so bad?
2) Is it that it is a huge capacitor or an bug inductive hole?
3) What techniqies could be applied to the layout to minimize
the issues relative these affects?
a) Don't put the copper rings on layers that do access the
signal as an example
b) Increase the anti-pad to reduce/change some of the
parasitics.
4) the list of questions is growing quickly...
Similar questions come up with regards to how to get to and from pcb lands.
The first question I'm really interested in is
What is the "long" list of questions I should be asking myself
when looking at interconnecting devices through multi-layer pcb?
And,
Any hints or experience in unraveling this list of questions would
be helpful. Rules of thumb often don't extrapolate well to these
limits, so actual data points or practical application of good
engineering techniques are really going to help.
Thanks in advance for any ideas or help!
Mark McKee
Cisco Systems.
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