[SI-LIST] : Clock skew

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Sun, 8 Nov 1998 11:59:05 +0200

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to avoiding clock skew between the clocks in my board, I connect eqaul
traces to all branches, to do so I tunning the trace with square (45
degres) loops
like that : _____/---\__/----\__/----\_______load.

1. do you think have any problem with this configuration ?
2. what is a resonanble skew between clocks ?

Best Regards
Shimon turgeman

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Next message: C.C. Chiu: "Re: [SI-LIST] : Trace impedance"
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