RE: [SI-LIST] : 66 MHz AGP Clock Signal

Chamseddine, Ahmad (ahmad.chamseddine@canada.cdev.com)
Tue, 14 Apr 1998 08:26:52 -0400

I thought that if you had high frequency signals, you would want to
route them in an internal layer between 2 planes to minimize radiated
emissions.
If you route the high frequency signals on layers 2 and 5, you really do
not solve that problem since these layers are just embedded microstrips
and are not shielded in any way. As far as signal integrity, if you
design your stackup to get the right stripline characteristic (Zo, Co)
then why use an embedded microstrip? I would very interested in your
comments and maybe some explanations of your experiments and results.

Sincerely,
Ahmad Chamseddine
Computing Devices Canada
email: ahmad.chamseddine@canada.cdev.com

> -----Original Message-----
> From: csoolan@dso.org.sg [SMTP:csoolan@dso.org.sg]
> Sent: Monday, April 13, 1998 9:46 PM
> To: Diaco Davari; si-list
> Subject: Re: [SI-LIST] : 66 MHz AGP Clock Signal
>
> At 11:58 AM 4/13/98 -0800, Diaco Davari wrote:
> >Hello,
> >
> >I've been working on a Intel based PC design, where I think
> >ringing/reflection on the
> >66 MHz clock to AGP (Video port) is going to be an EMC & Signal
> Integrity
> >issue due to long track lengths.
> >
> >We have used a 6 layer standard design layout of
> >Signal/GND/Signal/Signal/VCC/Signal, with all clock lines buried
> >interlayer. The fab house designs the geometry to control the stackup
> to
> >make the 65 Ohm on these critical lines. As you may already know,
> this 66
> >MHz clock line splits into two line which one loops back to the
> internal
> >PLL on the Intel chip and the other feeds directly to AGP port. Each
> >branch has its own damping resistor. According to design
> specification
> >both lines have equal length (Approx. 8 inch) but the loop back line
> is
> >cerpentined. The cerpentined feed back segment Placed interlayer next
> to
> >GND plane and placed right under the Intel chip. The clock line that
> >feeds AGP connector only switches once from inter layer plane A to B.
> >
> >According to the Emission data gathered with AGP video card in place,
> we
> >are still marginally above limit. We have already tried different
> values
> >of damping resistor at source and load side. Also, tried small value
> of
> >Caps on both ends to match the impedance of the line with source and
> >load, but no cleaner signal or better emission performance observed.
> >
> >Also, enabling the Spread Spectrum on clock generator has no effect
> on
> >the 66 MHz clock that comes out of the PLL section of the Intel chip.
> >
> >Does anyone know how to best resolve this Signal Integrity and EMC
> issue?
> >What is the best termination configuration?
>
> If you have split lines, normally the termination values are 2x65 Ohm
> at
> each end.
> Although the split lines are of the same width. (assuming).
>
> >What is the best layout design to cure this problem?
>
> It seems that you have 2 signals between the gnd and Vcc, this is not
> good for
> high speed circuits > 100MHz, I should think it will still work for
> 66
> Mhz. We normally
> recommend to have gnd and Vcc coupled together, S,S,GND,VCC,S,S
> 1,2, 3 , 4 , 5 ,
> 6
>
> The most critical clocks and lines are routed in 2 and 5. We have
> some
> experiements
> with signal integrity simulation that show the integrity will degrade
> if
> you put the signals
> in between the Vcc and Gnd.
>
> Good Luck.
> >
> >Best Regards,
> >
> >Diaco
> >
> >
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