When you talk about which plane the "signal is driven in reference to",
I think what you really need to think about is which plane the switching
current comes from. The reference voltage is important at receivers,
but not so much at drivers.
For CMOS and TTL, the current comes from the power voltage plane 50% of
the time, every time the driver switches high.
Forget voltages. Think currents.
Let's say an output is low, and the line has settled so there is little
current remaining. The driver switches high, by closing a "switch"
between Vcc/Vdd and the output pin. Current goes out that pin and into
the etch. Simultaneously, return current comes back on the reference
plane(s) surrounding the etch. If those planes are power planes, then
all is happy ... for this case of a low-to-high driven edge.
If one or both planes around the etch is/are ground, then you must get
the current coming back on the ground plane(s), into a current in the
Vcc/Vdd pins, to complete the circuit into the "switch" inside the
driver. You do that by bypassing the planes near the driving chip.
And the situation is reversed for high-to-low edges.
> if the signal is routed via vias in a dense board to use multiple power and
> ground planes as its reference, how do I assure or even model signal integrity?
> One suggestion is that at each via, a matching ground to voltage plane
> decoupling cap be added. Any ideas?
This really isn't any different than the situation at the driver, or at
loads that consume switching current. In either case, you must make
sure there is enough bypassing between your reference planes, to handle
the switching current that must pass from plane to plane.
Some of this bypassing is internal to the board, through the intrinsic
capacitance between planes. But that isn't enough when an IC switches
all its outputs, so we add capacitors at such "hot spots". A single via
by itself has enough bypassing around it so you don't need to add a
discrete capacitor. But a mass of vias, far removed from any ICs (with
their bypass capacitors), might need some help.
Even surface mount capacitors self-resonate at rather low frequencies.
At the highest switching speeds, they look like inductors, so you depend
on the intrinsic capacitance between reference planes in the board, for
those first few nanoseconds.
And yet, consider a via from one outer layer to the other outer layer
(as a worst-case scenario), with a number of intervening reference
planes. The return current of the transient edge, runs under the etch
on the first layer until it reaches the via anti-pad; and then it seems
to have nowhere to go! It spreads out around the via, finding an
increasing capacitance to the next reference plane down; and then to
the next plane; and so on, until it reaches the bottom reference plane,
where it re-forms as the mirror current under the etch there. If you
have picosecond edges, this is something to worry about. It's somewhat
similar to running etch over a reference plane split.
I've been told that east coast (USA) engineers equate vias with
capacitance, whereas west coast engineers say it's inductance. I've
wondered if it's the inductance of the via barrel itself, or of the
somewhat longer path the return current must take.