I've run into a similar problem (namely with ALTERA) with a die shrinkage.
Because of the new internal timing changes, existing rise and fall times
may not be compatible with new code, in that what was once fine with the
old PLD now causes a race condition to occur within the PLD itself. The
solution to this, is either to compile it with the "latest-and-greatest"
version of compiler/programmer, or do a mild code change. If there are a
lot of asynchronous signals, it is (usually) a good idea to make them
synchronous. Also, try running "Design Doctor" (or equivalent) while
compiling, and changing the code as to address the warnings.
Another issue that I've run into, is that the larger die was (typically)
more robust than the new. Conversely, the specifications on the new PLD
tend to be more stringent. Watch the currents on the inputs/outputs and
make sure they are in spec (it may be that you have to limit the currents
with a higher value input resistor). Connecting all unused inputs/outputs
to either ground or vcc is also a good idea (and where possible, tri-state
the unused pins internal to the PLD). In a lot of cases, you could
actually exceed the specs on the old PLD, while the new PLD won't allow it.
D. J. Hanna
Purge <firstname.lastname@example.org> on 19/07/98 03:48:49 AM
To: "Poulet P." <email@example.com>
cc: si-list <si-list@silab.Eng.Sun.COM> (bcc: David Hanna/Dalsa)
Subject: Re: [SI-LIST] : IC DIE SHRINK
Don't forget about the internal timing changing as well. I had a
problem a few years back with some FPGA's from Xilinx. They (Xilinx)
did a die shrink but didn't tell us so we happily continued to use the
old code image w/ the new die shrunk FPGA's. During some thermal
testing, we were continuously getting sporadic failures. After it was
all said and done, it turned out that the new FPGA's were at fault. A
quick recompile with the new compiler that supported the newer chips and
everything was fine.
Poulet P. wrote:
> Si list,
> My company once had a design working for several years until they shrank
> the die of a CPLD. Since then we had been experiencing sporadic failures
> and crashes until we found a solution. ( Terminating a few critical
> input signals ). So far not much new.
> My question is does any body know what could be the effects of a die
> shrink ( besides time delay and rise/fall time) on a component like a
> CPLD 2000 gates. I compared timing delays and rise time between the two
> processes and there were ( as claimed by the manufacturer ) almost the
> I could never get any clear answer from the manufacturer.
> Philippe Poulet
> RICOH Corp