Presently we have a CMOS ASIC design with VDD and VSS supplies
for the core logic and separate VDD and VSS supplies for
the I/O. I believe that historically the use of separate
supplies for the core and I/O was to keep the noisy I/O
supplies isolated from the core supplies.
Has anyone analyzed the problem to determine the benefit
or harm that would occur from using common VDD and VSS
supplies for both core and I/O - specifically as it
applies to today's submicron/million+ gate ASICs? Any
designs out there that worked with common supplies
to core and I/O?
We are presently evaluating a package that will have low
inductance VSS path but a high inductance VDD path. With
common supplies on the chip we could use the core's VDD to VSS
capacitance to lower the AC impedance of the VDD supply
and thus reduce switching noise when switching from
LOW to HIGH.
Mike
-- _______________________________________________________________ Mike Degerstrom Email: [email protected] Mayo Clinic - Gugg. Bldg. RM 1011-B Phone: (507) 284-3292 Rochester, MN 55905 FAX: (507) 284-9171 WWW: http://www.mayo.edu/sppdg/sppdg_home_page.html _______________________________________________________________ **** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****