Re: [SI-LIST] : ASIC noise update....

D. C. Sessions ([email protected])
Mon, 06 Apr 1998 10:44:09 -0700

Lfresearch wrote:

> When I did my measurements, I recorded that the ASIC outputs changed state
> between 1 and 2 ns, this is way too fast for my needs, is there any LOW COST
> way to selectively slow down a transition by an order of magnitude?

With a transition time of 1000-2000 ps, it sounds like
the outputs have already been slowed down to an extreme degree.
It's possible to design predriver circuits that produce
very slow output transitions (eg, USB) but it's not easy;
the designer has to do some pretty extreme tricks to
avoid crowbar current and still get the turkey to switch.

If you're using a standard-cell chip you *might* get the
library shop to crank a custom-but-anyone-can-use-it cell.
If you're using a gate array your only option is to use
very-very-weak drivers and let the di/dt scale appropriately
while reflections stairstep the output to its final value.

D. C. Sessions
[email protected]