Re: [SI-LIST] : tying clock outputs to reduce skew?

Vinu Arumugham (vinu@cisco.com)
Wed, 15 Apr 1998 14:26:44 -0700

PETER_ARNOLD@hp-santaclara-om3.om.hp.com wrote:

> We're thinking about tying some or all of the 100MHz outputs of a
> Motorola MPC952 clock generator together into a single node, and
> distributing a clock from there to various loads via series
> terminator. The idea is to eliminate output-to-output skew by
> combining all into a single waveform. I think that if the inter-output
> traces are kept short enough, it ought to behave as a passive mixer of
> all the clocks. Motorola has heard of this being done, but has no
> advice to offer.
>

We have used this in many designs and it works well.

> One hazard is that a voltage differential exists between skewed
> outputs during edges, giving rise to a small current flow out of one
> pin into another, but I think this should be small.

The first of the skewed outputs will see a large load and slow down, letting
the other outputs catch up. The voltage differential is therefore likely to be
even smaller in this case than on a device used in a conventional clocking
scheme.

>
>
> Can any si-list experts offer advice on this technique?
>
> peter arnold.