I'm not sure there are a whole lot more hits to give as far as USB goes, and
I'm sure others on the list can do a better job with respect to LVDS than I.
USB signal traces are strictly point-to-point, with all fan in/outs done in
silicon behind the USB transcievers, so there's no reason you'd route a Y on
the data lines.
NRZI is just non-return to zero inversion coding---you can implement it on
almost any signaling technique, regardless of wether it's faux differential,
true differential, or single ended. For USB's implementation of NRZI and
USB signaling and termination details, download the 1.1 USB spec from the
tech docs section of www.usb.org/developers/, if you haven't already done
so.
If you have other USB implementation questions, please post to the USB
developers webboard (you can find it at the URL above) or email just me
directly; we're getting off-topic as far as SI-List goes.
Todd
-----Original Message-----
From: [email protected] [mailto:[email protected]]
Sent: Thursday, November 05, 1998 7:09 PM
To: [email protected]; [email protected]
Subject: Re[2]: [SI-LIST] : USB & LVDS Differential signals routing
Todd,
I much appreciate you for your valuable information. Would you mind
to
give me more hints about faux differential and NRZI differential signals? I
don't get the points of the difference between them. Would you please
explain
if it is matter to route "Y" topology, which has long stub for USB? Will
the
reflection cause malfunciton of USB?
Thank again,
John Lin
CAE Manager at Arima Computer Corp.
______________________________ Reply Separator
_________________________________
Subject: RE: [SI-LIST] : No subject given
Author: "West Todd" <[email protected]> at INTERNET
Date: 1998/11/5 06:45 PM
John,
I won't claim to be a layout wizard (mostly, I know enough to get myself in
trouble), but perhaps I can shed a bit light on the matter.
Probably the most important thing to realize is that USB is actually *not*
differential signaling---both of the data lines have single-ended drives to
ground, rather than the single drive loop of true differential systems such
as LVDS. As a result, USB is perhaps better called faux differential. The
voltage swings on the lines still look like NRZI differential signaling, but
it's possible to have skew between the data lines from differences in the
driver turn-on times that simply can't exist in a truly differential signal.
So, as far as USB is concered, both the single-ended and differential
impedance matters. However, USB's edge rates are relatively slow (7--26ns
in practice) and well controlled, so the bus is really quite robust in the
face of impedance glitches (which is a good thing, since many USB developers
are new to transmission lines).
As to stripline trace width and spacing, I use the single-ended formulas
found in the back of _High-Speed Digital Design_ and the differential
formulas for side-by-side traces above a ground plane published by National
Semiconductor in their LVDS design guide (see
www.natsemi.com/appinfo/lvds/index.html).
What I have yet to determine to my satisfaction is the range of trace widths
and geometries over which these formulas are valid---how wide, how far above
ground, how heavily buried by soldermask, etc. were the test traces used to
come up with them? Anyone know for sure? I assume they'll work pretty well
for a typical SPGS four layer board stackup with the controlled impedance
signals routed next to the ground plane on a 6--8 mil dielectric, but some
USB devices are simple enough they can actually use two layer boards. A
straightforward application of the formulas there comes up with 130mil wide
traces 700mils apart for the usual 62mil FR4 thickness!
Todd West
Intel/USB-IF
[email protected]
-----Original Message-----
From: [email protected] [mailto:[email protected]]
Sent: Thursday, November 05, 1998 5:31 PM
To: [email protected]; [email protected]
Subject: [SI-LIST] : No subject given
Hi all SI experts,
Does somebody know how to determine the trace width and trace spacing
for differential signals such as USB or LVDS?
For example, the USB signal, Intel recommands 45 ohms for single
trace impedance and 90 ohms for differential impedance. I find 12mils
for trace width and 32mils for space for my pcb stackup will meet the
spec. Also I find 6 mils width and 8 mils spacing will also meet 90
ohms differetial impedance but 58 ohms for single trace.
I believe that all I need to take care is 90 ohms differential
impedance instead of 45 ohms for single trace. Am I right?
What will be different between them (12x32 and 6x8)?
I think that the spacing of 32 mils is too big because the
differential pair shall be routed closely to cancel common mode noise.
Are there any disadvantages for high single trace impedance but same
diffential impedance?
Can we have long stub topology, such as "Y", for the differential
signal routing? Shall the reflection on the pair be cancelled because
of common mode cancellation?
Thank you for your reply in advance.
John Lin
CAE Manager at Arima computer corp.
Email: [email protected]
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