[SI-LIST] : Substrate modeling

R.S.Krishnan (rsk@cypress.com)
Thu, 19 Nov 1998 12:21:04 +0531

Hi,

I have a Clock chip design that has some Clock outputs on
its VSS pin(s) and the rest of the outputs on a different VSS pin(s).

On Silicon, we have observed that there exists interaction between
these sets of outputs. The VDD of the outputs are separate too.
The two sets of VSS pins are not connected on chip (except through
the psubstrate). I would like to know how to model this substrate
connection between the two VSS.

Thanks
Krishnan

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