Re: [SI-LIST] : power supply filtering and bypassing

John Fisher ([email protected])
Thu, 05 Mar 1998 17:28:56 -0800


If at all possible find out what range of low frequencies that the PLL is
sensitive to and then evaluate the response of your low pass filters. You
may be unpleasantly surprised by the response of the Mfgr's recommended
filter design.

Good luck

John M. Fisher -- Cisco Systems -- [email protected]
170 W. Tasman Dr., Bldg G, San Jose CA 95134-1706
__ _ _
________/// \_/ \________/ \ ____
Signal Integrity Engineer, Enterprise Line of Business
408-527-9186, Fax 408-526-5504, N6PFN
At 02:41 AM 3/5/98, Skey, Kevin wrote:
>I was browsing the web and happen to bump into this discussion group. The
>discussions look to be pretty broad, so I hope by me being specific
>doesn't violate the scope of the group.
>I've been working with a high-speed (1Ghz+) point-to-point data link
>chipset from HP called GLINK (HDMP-1022/HDMP-1024). Both receiver and
>transmitter have built-in PLLs used for Transmit Clock generation and
>Receive Clock extraction.
>The application is PC based so I've been having problems attempting to
>use off-the-shelf ATX PC switching power supplies.(i.e. 250W ASTEC) I've
>discovered that the supplies have horrible (under and over shoot)
>transients ([email protected]) causing loss of lock on the receive end. I
>guess I shouldn't expect a lot for 30 bucks!!
>The noise seems to correlate with disk accesses mostly (but even mouse
>movement shows up), so I'm guessing the supplies have a regulation
>problem with variable loads. I haven't gone as far as looking spectrally
>at this because I'm not sure what frequencies and DB levels would cause
>resonance and/or phase problems in the GLINK . I'm guessing this noise is
>coupling in on the TX PLL causing enough/or right frequency jitter so
>the receiver PLL loses track. If I cut the boards VCC line and wire in a
>linear supply(don't use the PC's VCC, but use the GND), the link stays
>solid. The only supply filtering recommendation from HP is the catch-all
> 0.1uf bypass, but this doesn't seem suitable, so I ask the following.
>What is the best way to measure the frequency content of the noise?
>Any good reference articles or papers for this situation?
>I'm planning a layout change, separating the GLINK's power and ground
>layer from the rest of the PCB and use a pi filtering arrangement to
>connect the planes, I'm not sure what filter values would be acceptable
>or if this is the right approach at all, any ideas?
>Kevin Skey
>Northstar Technologies
>[email protected]
>978-897-6600 x168