It's a little more complicated than that. The 5v pulldown spec is stronger
than the 3.3v spec because the 5v is presumed to have to pull a line down
from 5.5v to near ground in the same time that a 3.3v driver has to pull the
same line down from 3.6v. In practice, the 5v-tolerant 3.3v drivers only
have to do this on the first cycle after a turnaround. Beefing up a 3.3v
driver to meet the 5v specs actually results in unacceptable signal
integrity the rest of the time.
> The spec for 3V devices is for those devices in a 3V signaling environment.
> A 3.3 volt component in a PCI bus designed for a 5V signaling environment must
> meet the 5V requirements. The 2.4 V, 0 A, operating point is only the minimum
> allowed by the spec. Only a bipolar device operating at 3.3 volts would ever
> approach this minimum. I have never seen a bipolar PCI device. However,
> a 3.3 volt cmos device operating on a 5V bus, will, of course have an Iol=0 at
> 3.3 volts. This causes problems with mixed 5V/3.3V devices on a bus.
> The 5 Volt PCI spec does not require clamps on the high rail. For a 5V only
> system, this does not usually pose a problem, because, even with high ringback,
> there is ample margin around the nominal 1.5V switching threshold.
> However, when a 3.3 V device drives in a 5V signaling environment, ringback will
> often occur within the input threshold region. Generally, this is where we
> signal integrity engineers make our money on the PCI bus. The original
> implementers of the spec left out a few details in how to make these mixed
> systems work over worst case. Often they don't work in the typical case.
That's why the pullup V/I for 5v tolerant devices MUST be the 3.3v ones,
never mind the literal interpretation of the Intel scriptures; it's also
why the pulldown curves should be only slightly modified from the 3.3v ones.
Strictly speaking, the 3.3v curves are best *provided* that the output
timing can still be met when driving a line charged to 5v following a
turnaround. This is often not a matter of I/O design but of core logic
optimization, making sure that turnarounds aren't unnecessarily delayed.
If that doesn't work, the I/O can be modified to have increased drive
when pulling down from higher voltages, still within the PCI spec.
> > The worst case high state vi curve in the PCI spec shows Voh=2.4v for
> > I=0 to 2mA (Figure 4-3, VI curve for 5V signaling). Section 4.1.2 of
> > the PCI spec says that "PCI is a CMOS bus", which would mean that Voh
> > should be close to the rail (note that Ioh &IiL ~ 70uA per the PCI
> > spec.) Granted, 3.3v devices are allowed to drive in a 5V environment,
> > and specs for 3.3v parts do say that Voh_min=2.4v but isn't this a
> > holdover from the TTL / Bipolar days?
> > The difficulty arises in meeting the PCI spec of Tpd_max = 10nsec (due
> > to ringback).
> > Does anyone know of PCI devices that actually put out 2.4v at I=0 amps
> > (high temperature, low supply voltage) or is the spec just too worst
> > case?Note that I also question Vol=0.55v at I=0amps for the low state vi
> > curve as well.
IMNAAHO, this is why signal integrity engineering needs to be moved up in
the design cycle to the chip-design stage or, ideally, even earlier to the
library-development stage. Then again, that's what VLSI hired me to do.
-- D. C. Sessions email@example.com