Based on the package correlation (measurement) work I did when supporting
the Alpha processsor and its core logic ASICs at Digital, the effect of the
stub (the additional capacitive loading, the reflection caused by the open
ended T-line,etc.) seemed to be negligble above ~1 nS edge rates, but
noticeable at 0.75 nS and below.
With a good extractor that 'does the right thing' you can easily verify
when you need to consider: a) the effects of the stub and take them into
account and/or b)the effect of 'pin-swapping' a short trace/long stub net
for a long trace/no stub trace.
/Greg
At 03:49 PM 10/7/98 +0900, komerix wrote:
>Hello All,
>
>I am simulating BGA platting patterns.
>
>In my thought, there aren't any tools that could condsider plating patterns.
>I also modeled this patterns with one material, copper.
>But, I can't affirm that this would have litttle error.
>Could anyone tell me how much deviations exist between measurement and
>simulation result?
>I will appreciate any information about this.
>
>Sunhue HUH
>
>## Komerix Engineering. ##
><huh>[email protected]
>
>
>
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>
>
Greg Fitzgerald
Cadence Design Systems
Performance Engineering Business Unit
270 Chelmsford, MA 01824
Phone: 978-446-6638
FAX: 978-446-6798
e-mail:[email protected]
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