RE: resend the question. (The Criteria of overshoot, undershoot, RingBack for different logic types

John Lin - TAO ()
Mon, 14 Jul 1997 08:59:49 +0800

Hi Andy,

I agree your points about ringback. If the ringback won't cause any
misjudge in logic level, the ringback in not harmful.
However, Generally speaking, big overshoot will cause big ringback.
The overshoot is a kind of "STRESS TEST" for device itself. For long
run, It will cause reliability issue for the device. Also the big
undershoot will cause latch-up problem and burn the device.

I think that the over/undershoot is more harmful than the ringbacks for
a logic
device.

The ringback here is the magnitude over the supply voltages(VCC and
VSS). Therefore the ringback 0.8v for LVTTL (3.3V) is about 2.5V (=
3.3-0.8) for overshoot ringback. and 0.8V(=0+0.8) for undershoot
ringback.

Thanks,

JohnLin -TAO
CAE Engineer of the EDA Department.
DEC Taiwan Branch,
Email: Linjohn@mail.dec.com
TEL: 886-3-3900000 ext. 2565

>----------
>From: Andy Ingraham[SMTP:ingraham@wrksys.ENET.dec.com]
>Sent: Friday, July 11, 1997 6:49 AM
>To: John Lin - TAO; John Lin - TAO; si-list@silab.Eng.Sun.COM
>Cc: si-list@silab.Eng.Sun.COM; ingraham@wrksys.ENET.dec.com
>Subject: RE: resend the question. (The Criteria of overshoot, undershoot,
>RingBack for different logic types)
>
>John Lin,
>Regarding your criteria, I would say that 0.8V for ringback is
>way too much for TTL and LVTTL, if you define ringback as the
>magnitude that the voltage crosses back past Vih(min) or Vil(max).
>0.3V or less, sounds better. Regular 5V CMOS can probably
>tolerate more.
>
>Keep in mind that ringback generally doesn't matter until the
>point in time when you need your inputs to be stable. That is,
>if it is a data (non-clock) signal, there will be Setup and Hold
>times that must be observed. Outside of the interval between
>them, the input can ringback any amount and it may make no
>difference (unless it causes metastability that doesn't stop
>once the input stabilizes; or if the input sits right around
>threshold and causes excessive currents from VDD to VSS).
>
>Regards,
>Andy
>