[SI-LIST] : Priority of test pads

Tim Parks (tparks@ferrotec.ie)
Fri, 04 Sep 1998 12:56:38 +0100

Dear all
our company has designed an embedded system PCB consisting of two
microprocessors, DRAM, VRAM, Flash, UART and analogue subsystem. There are
a total of 3000 nets and in an ideal world we'd like to attach a test pad
to each net. But space issues (it's a hand-held product) prevent us from
doing this.

The production house can use TestJet capacitance tests on all IC's and
Connectors for joint integrity test. Also function tests will be of 74
series IC's and RAM verification if requested.

I'm looking for guidance in the prioritising of test points. Do we need to
checker-board test RAM? &$ series etc...

Any help appreciated
Tim
_____________________________________________________
Tim Parks
Technical Manager
Ferrotec Ltd
Unit T9
Maple Avenue
Stillorgan Industrial Park
Stillorgan Tel: 00-353-1-2952529
Co. Dublin Fax: 00-353-1-2953625
______________________________________________________

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