Re: [SI-LIST] : SI openings at Stratus else delete -- OBJECTIONS ...

Gary Fowler (analog@sprintmail.com)
Tue, 17 Feb 1998 10:20:09 -0500

Murali Raj wrote:
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> This is absolutely outrageous.
> I strongly object to this.
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> Please do not make spoil the sanctity
> of a group to which people sign on for
> information and knowledge exchange.
> Not for receiving, as you very mildly put it,
> "junk mail".
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> Its people like you who give the web a bad name.
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> I hope you desist from such activities in the future
> and start using ethical means of finding people
> to work in your organization.
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>=20
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> On Thu, 12 Feb 1998 Steve_Mango@stratus.com wrote:
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> -->
> -->Sorry for the "junk" mail... but if any of you signal fidelity engin=
eers
> -->are available... please read on:
> -->
> -->=3D=3D=3D=3D
> -->
> -->My name is Steve Mango and I am the hiring manager of the Analog and
> -->Signal Fidelity Group at Stratus (a fault tolerant computer design
> -->company) in Marlboro, Ma. I have openings for signal fidelity engin=
eers
> -->to join my fast-growing team. I would prefer full time permanent
> -->engineers, but I am willing to consider contractors.
> -->
> -->My group must solve many high-speed technical challenges as we push
> -->clock and bus speeds >100MHz. I am looking for experienced signal
> -->fidelity engineers to broaden my group. [Note: These positions are =
for
> -->USERS of signal fidelity tools to solve complex problems, rather tha=
n
> -->for software developers of new software analysis tools.]
> -->
> -->* Help define/diagnose/solve complex signal fidelity problems (clock
> -->generation/distribution, interconnect design, timing, termination,
> -->decoupling, power/ground distribution, package/connector selection,
> -->etc.).
> -->
> -->* You should have at least 3-5 years experience in the signal fideli=
ty
> -->and high speed digital design field.
> -->
> -->* You should have hands-on experience with modeling and simulating w=
ith
> -->Quad Design tools (MOTIVE, XTK, TLC), SPICE (PSPICE and HSPICE),
> -->electromagnetic field solvers (e.g., Greenfield, Pacific Numerix,
> -->Maxwell 3D, etc). Candidate should be familiar with high speed board
> -->interconnect routers (Allegro and CCT router preferred). Experience =
with
> -->IBIS modeling and Interconnectix software is a major plus. Candidate
> -->should also be familiar with high speed test plan development, test
> -->measurements techniques and lab equipment (HP and Tektronix). Experi=
ence
> -->with current high speed processors and multiple logic families is
> -->desirable. Other pluses are experience with custom ASIC cell design,
> -->phase lock loops, hot plug, FET switches, PCI Bus, SCSI bus, and
> -->web-based documentation.
> -->
> -->=B7 Education: BS degree minimum.
> -->
> -->It=92s an exciting time here at Stratus
> -->
> -->Come Join our team.
> -->
> -->Please call me at (508) 490-6231
> -->Or email me at: Steve_Mango@stratus.com
> -->
> -->
=20
Raj,

As a "Headhunter" who specializes in EMC and Signal Integrity engineers
I understand where you are coming from here. I have not, nor would I
choose to post searches on the si-list. However, I have only seen
these types of postings once or twice within the last year. Also, I
would advise you that information of this type will never hurt you. You
never know what the future may bring. Contacts are everything in this
business world.
--=20
Gary Fowler
Analog Solutions=20
7 Heather Trail=20
Rochester, NY 14624=20
716-426-2647 * fax-716-426-2649=20

http://www.analogsolutions.com