Re: [SI-LIST] : SSO noise: Through current vs. Discharge current

Jose Luis Gonzalez Jimenez (
Tue, 30 Sep 1997 09:42:11 +0100

>Several weeks ago I asked a question to the list concerning
>simultaneous switching noise (SSN). I received many useful
>answers. Most pointed me towards Senthinathan and Prince,
>which I have ordered, but not yet received.
>One issue that concerned me was the influence of load
>capacitance on the SSN. The answer, it seems, depends on
>the design of the output buffer:
>1) If the P and N transistors are momentarily ON,
> then the "through" current dominates, which means that
> the maximum noise amplitude is independent of the load.
> This is because the di/dt of the through current is greater
> than the di/dt of any (dis-)charge current.
>2) If the output buffer is designed so that the P and N
> buffers are never both ON, then the SSN source
> is predominately the (dis)charge current. SSN increases
> with Cload up to a certain value of Cload, then plateaus
> off (Vmax).
> If the Cload is replaced by a transmission line, then
> then a simple rule is that the SSN is (Iz/Isc)*Vmax,
> where Isc is the short-circuit output current and Iz is the
> output current for a resistance equal to the impedance of
> the line.
>This interpretation prompts the following question:
> Are real-life buffers designed such that the P and N
> transistors are never ON simultaneously?
Again, it depends on the output load. If the actual output load is samaller
compared with the target output load of the buffer the output falling and
rising times will be shorter than expected and the P and N transistors of
the last stage of the output buffer would be ON temporally. The question is
the ratio between the output's and the input's slopes. However there have
been proposed many techniques to suppress short circuit current in the last
stage of the output buffers by a more complex driver than a simple big
inverter. See i.e. IEEE J. Solid-State Circuits (JSSC) Vol. 28 (12), JSSC
Vol. 29 (3), JSSC Vol. 29 (11), JSSC Vol. 32 (1), JSSC Vol. 32 (6).

I hope this helps!

Jose Luis Gonzalez


O O O Departament
O O O d'Enginyeria
O O O Electronica

Departament d'Engineria Electronica
Modul C4, Campus Nord
c/. Gran Capita s/n 08034 BARCELONA (Spain)
telf. + 34 3 4016748
+ 34 3 4017476
fax. + 34 3 4016756