RE: [SI-LIST] : A timing question in high speed bus

=?iso-8859-1?B?wfXK97Hy?= (liushb@263.net)
Thu, 19 Nov 1998 11:17:00 +0800

I wrote this mail yesterday , but for some reason that I do not know, it
seems that the mail was not sent , so I sent it again .
My design is not a source synchronous clocking scheme. The clock souce
must be on one of the daughter boards and be driven to others and of course
the clock on each daughter board should be synchronous . And the bus is to
be a share bus , the data both may be driven from the clock daughter board
to the others , and may be driven from the others to the clock board . So I
think I have to take the flight time into account.
Is the part SN74GTL16622 not faster enough ? Why the NESA's paper "An
Innovative Distributed Termination Scheme for GTL Backplane Bus Designs"
says that their design use GTL+ (The author mentioned SN74GTL16622 in the
references)? And Intel's "100MHz GTL+ layout Guidelines for the Pentium II
Processor and Intel 440BX AGPset" is also using GTL+ part ? If the 16622 can
not do the work , does anyone such as 16923 can do it ?
Thanks .

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