Re: Separate +5V Plane

[email protected]
Thu, 27 Mar 1997 20:34:22 -0500 (EST)

The last few years has seen a jump in techniques that out pace text books:
some of the benifits from techniques you discussed could be missed if you
take the literal context.

I keep a seperate ground for Digital circuits and Analogue circuits, mainly
because it helps keep the emissions down. I design microcontrollers that have
plastic cases and have to meet CISPER 22. Keeping micro, ASIC, FPGA and
memory switching noise away from my interface wiring is essential: having a
common ground substantially raises the emissions. One area where I take
special care is where the A to D is. I cannot afford a 16 bit convertor, so I
have a single slope integrator one implemented. The Comparator outputs are
located near the point where I tie A and D gnds together.

Providing seperate planes for each IC has been tried, but to only limited
succes in my case. I suspect that the nature of my traces prevents this
method from getting good results. Two chaps in MN have published papers on
this topic at the EMC Symposiums, and I'm sure I have copies somewhere. I
believe the term is "micro-island". If you need to know more I could try to
dig them out.

Please let the list know how you go on.

Best regards,

Derek Walton.
L F Research EMC test facility

PS Anyone know of a good way to share graphics over the mailing list? Would
allow me to distribute some emission curves.