Re: [SI-LIST] : Modeling connector pin vias

Dr. Edward P. Sayre (esayre@nesa.com)
Wed, 29 Oct 1997 16:38:12 -0500

Yes, some people have reported success in doing that which you suggest.
Unless you have a good electromagnetic model of the via and the
power/ground plane capacitance, it will be difficult to "tune out" the
vias. They are also negligible at logic device risetimes. The reflection
coefficient is a function of dV/dt, so what shows up at 35 - 50 ps, is
considerable reduced and broadened (the area is preserved under the
reflection curve) at 300 - 400 ps risetime.
Also, the via capacitance can be used to tune out the pin inductance.

Hope this helps.

ed sayre
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At 10:26 AM 10/29/97 -0800, you wrote:
>Item Subject: cc:Mail Text
>
> I am interested in modeling vias for through-hole connector pins in a
> multilayer controlled impedance board.
>
> I have found that I get lower TDR impedances on bussed signal traces
> routed to several connectors than for a simple test trace of the same
> geometry. This is true even on a bare board with no connectors or
> other components installed.
>
> The lower impedance appears to be due to parasitic capacitance of the
> feedthroughs and associated pads and PWR/GND planes. Signal rise times
> in my application are about 1-1.5ns, so it seems reasonable to model
> the vias as an excess lumped capacitance at the connector pin nodes.
>
>
> My guess is that pin capacitance is a function of connector itself
> (which the connector manufacturer may provide a model for), as well
> PCB parameters such as thickness, number of layers (including PWR and
> GND planes), pad size and clearance to plane layers.
>
> Does anyone know of a calculation tool or formulas to get an
> equivalent lumped via/pin capacitance I can use with a transmission
> line simulator?
>
> Also does anyone have experience with the technique of clearing a
> rectangular region of metal in the PWR/GND layers around the connector
> signal pins to reduce excess capacitance? In my application, which
> uses differential signals, the increased impedance and loop area for
> common mode GND currents should be less troublesome than for single
> ended signals.
>
>

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