First off, adding caps to I/O pins is often counterproductive.
It increases the transient supply current, often dramatically
because the drivers which previously faced a resistive load
(Tline) to a capacitive one where the current is limited only
by Idsat.
Which leads into the other key issue: grounding. In my
experience the vast majority of EMI and ESD problems are
tracable to poor power/ground practices. For instance,
if your ASIC uses a common path for core and I/O power and
ground core transients will show up on the I/O rails and
consequently the pins. Another despicable but common
practice is using an I/O cell in the padring as a clock
driver for the core, so that ALL of the clock return
current flows through the driver->PWB->core path, making
two passes through the supply inductance.
Which in turn brungs up the question of packaging. You
don't say what kind of package you're using, although for
relatively low-performance designs I'd guess PQFP. They're
nasty, with as much as 18nH on each supply pin and all
too often not enough supply pins.
> Could any of you please throw some light on this issue? Is there any
> thumb rules that we can follow to supress RFI for such end products?
Grounding, grounding, grounding. Keep the return paths
short for your signals, esp. clock -- and that means the
paths INSIDE the package too. Once you've done that, you
can quiet things further by adding bypass inside the part.
Even gate arrays can be improved by tying the spare gate
inputs to ground; that adds the PMOS gate capacitance of
the spares to the power-ground loop.
For REALLY quiet operation you should limit the oscillator
current. Most CMOS oscillators are too robust for their
own good and pull a lot of current in the linear range.
If you isolate the oscillator supplies from the first-stage
amplifier, you can add a current-limiting R/C network
(symmetrical to the rails) to the oscillator and keep it
from banging around quite so hard.
> Besides this, could any of you please advise, what are the EMC
> fundamentals that we should consider while we deisgn the CMOS ASICs
> that has the gate count of less than 12K and runs at 12 to 24MHz?
Maintain strict separation between the core and I/O supplies;
especially with regard to clocks. If possible provide
separate supply connections for the predrivers too, since
they are a good intermediary between the core and I/O.
Above all, mind the return paths: they are the root of
all evil.
-- D. C. Sessions [email protected]