Csaba Csaszar (email@example.com)
Thu, 08 May 1997 22:19:26 -0400
I have to design a continuously variable delay line for an ECL ~ 500MHz
frequency clock signal. The delay should be 0.5..2.5ns. The size of
the circuit must be below 1x1 inch. I was thinking to use the
conventional passive delay line configuration (T) with Variac diodes,
but needed 3-4 stages.
Could some one advice me a smaller better solution??
Thanks, Csaba Csaszar