Re: [SI-LIST] : Excessive clock overshoot]

Todd Westerhoff (toddw@lineage.com)
Fri, 15 May 1998 18:37:07 -0400

At 12:48 PM 5/14/98 -0500, Dennis Tomlinson wrote:
>
>Message-ID: <355B2022.2EED0E7@tellabs.com>
>Date: Thu, 14 May 1998 11:47:30 -0500
>From: Dennis Tomlinson <det@tellabs.com>
>X-Mailer: Mozilla 4.04 [en] (X11; I; SunOS 5.5.1 sun4u)
>MIME-Version: 1.0
>To: fabrizio=zanella%eng%emchop1@fishbowl02.lss.emc.com
>Subject: Re: [SI-LIST] : Excessive clock overshoot
>References: <vines.8VJ8+h7iKpA@fishbowl02.emc.com>
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>
>fabrizio zanella wrote:
>
>> I apologize for not giving enough information on yesterday's email about
>> the FCT clock overshoot. The termination at each end of the bus for these
>> clock lines is thevenin 100-5V/220-gnd. The loaded round trip delay is
>> about 4.4ns, so 2.2ns one way.
>> Hope this helps, thank you very much for the comments thus far.
>> The comment from Andy Ingraham about the FCT clock resonating at 45MHz does
>> make sense because on a receiver card at the clock input we see
>> oscillations/non-monotonic signals.
>> Would the resonance be caused by the internal clock circuitry or the load
>> it's driving?
>
>The resonance is due to transmission line effects - aggrivated/complicated by
>all the loads hanging off of it (including the driver). As the clock
frequency
>
>increases, it's half period approaches one round trip delay on your clock
net.
>
>Since your load is under terminated (about 69 Ohms - causing a load
reflection
>of
>+0.47) and your source is over terminated (roughly 10 Ohms - causing a
>source reflection of -0.43), you're experiencing the T-line equivalent of
>oscillation known as standing waves. Reflected waves are arriving at the
>driver
>in phase with the driver output signal swings. Then, about 1/4 cycle later,
>they add
>in phase at the last receiver (and in part, bounce back toward the driver,
>etc.).
>
>The fix is to decrease the reflections. One crude but effective method might
>be
>to add a clamp diode to the upper rail at the receiver furthest from the
>driver.
>
>Another method would be to decrease the resistor values in your Thevenin
>termination to something closer to a 25 Ohm equivalent. The strength of
>your driver will probably limit how low you can go.
>
>Another method you could try is AC termination. On long clock nets like
>yours,
>using a bypass capacitor in series with 30 to 40 Ohms might give enough
>damping.
>The bypass will charge to the average voltage, thus emulating a balanced
>Thevenin termination. (Note: there's no power to be saved by using a smaller
>capacitor on a net this long at this frequency)
>
>Your 100/220 termination gives 3.44V for V-Thevenin. Was there a reason for
>this termination voltage? If R-Thevenin is decreased to 25 Ohms, but
>V-Thevenin remains the same, it will take about 130 mA. to drive a logic
>'0' into this load.
>
>Also, was there a reason you're using 25 Ohm routes instead of something
>higher? Lines with Z0 this low are hard to drive. Switching currents
required
>
>of the driver must be over 125 mA. to change the T-line's state.
>
>Best of luck,
>
>Dennis
>
>>
>>
>> Regards, Fabrizio Zanella.
>> EMC Corporation
>> fzanella@emc.com
>> -------------
>> Original Text
>> From: "D. C. Sessions" <dc.sessions@vlsi.com>, on 5/13/98 5:23 PM:
>> To: smtp@Eng@EMCHOP1["SI-List" <si-list@silab.Eng.Sun.COM>]
>> Cc: smtp@Eng@EMCHOP1["SI-List" <si-list@silab.Eng.Sun.COM>]
>>
>> fabrizio zanella wrote:
>> >
>> > I have a question regarding an FCT clock (TTL levels) driving a heavily
>> > loaded backplane. On the driver pin we see excessive overshoot on the
>> L-H
>> > transition which increases as we increase the clock frequency. This
>> > overshoot goes from 5V at 33MHz to 6.5-7.0V at 45MHz. The stub impedance
>> > is 75 ohms, backplane impedance 25 ohms loaded. There is a clamping
>> diode
>> > on the H-L side but not on the L-H. The H-L side does not have any
>> > undershoot.
>> > I have asked the manufacturer and they have never seen this phenomena,
>> nor
>> > do they have an explanation for it.
>> > Any ideas on what could be causing this?
>>
>> 1) Is the line unterminated?
>> 2) Is the loaded one-way delay anything near 2.7ns?
>>
>> --
>> D. C. Sessions
>> dc.sessions@tempe.vlsi.com
>
>
>
>
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