No, I'm sorry that I don't have a good reference on ISI. My communications
theory is several decades old, I'm ashamed to admit. Fortunately, the
information once gained resonates softly in the background as I
do digital baseband simulations.
I don't have any analytic expressions for ISI, although I do have some
simple rules of thumb:
(well, having written this, i find that i do have a "few" expressions that
may be useful.)
If we assume a perfect "fixed" timing threshold, and we know the
the received waveform ramp rate through the threshold region, we
can compute the relative change in timing due to any signal level shift.
(A signal level shift can be due to a DC signal offset, injected noise riding
on the signal, noise at the receiver, power and ground noise, DC ground
reference shifts from source to receiver, signal integrity effects ... etc.)
1) timing sensitivity to offset = (delta t)/(delta V) = 1 / slew rate
For example, if the slew rate in the receiver threshold region is
1 V/ns, then the timing sensitivity to offset is 1ps/mv. A signal
with a faster slew rate such as 4 V/ns would have a timing sensitivity
to offset of .25ps/mV.
Using the timing sensitivity to offset we can compute the sensitivity
to rising edge/falling edge starting point asymmetry. That is, imbalance of
the wavform around the reference point, a common problem with non-differential
2) timing sensitivity due to asymmetry
=ABS( (Vhigh - Vthresh) - (Vthresh - Vlow)) / slew rate
=ABS(Vhigh +Vlow - 2 * Vthresh) / slew rate
Again, for a hypothetical bus with a signal slew rate of 1V/ns a
receiver reference threshold (Vthresh) of 1volts, a Vlow
of .4 volts and a Vhigh of 1.5 volts, the timing sensitivity
due to asymmetry would be:
ABS(1.5 + 0.4 - 2 * 1) * 1ps/mV = 100 ps
A simple way to view this is that 100 ps of rising edge/ falling edge
jitter occurs because the initial starting points of the two edges
are different. Open collector signalling systems without feedback are inherently
unbalanced in this way. Vhigh is set by the termination voltage. Vlow
is set by the output impedance of the driver, which can change over
process and temperature.
These equations are profound. They can be used to very closely
"ball park" the bounds of timing jitter due to many different sources
other than signal swing asymmetry. They can be used to quantify the
following effects on jitter rather closely:
dc signalling losses due to I/R drop
ac signalling losses at frequency due to dielectric and skin effects
termination voltage tolerance effects
termination resistor tolerance effects
receiver threshold voltage shift
termination voltage loss due to I/R drop
ground/power plane voltage shifts due to transient response
ground/power plane to signal flux coupling
common mode noise
differential mode noise
sso device/package noise at driver
sso device/package noise at receiver
Of course, I assume that one can quantify all the other effects accurately.
Given the equations 1 and 2 above, any signaling effects which change
the starting point of a rising or falling edge waveform will cause edge
jitter. This is technically ISI. One symbol interferes with another.
Overshoot, undershoot (negative overshoot), and ringback which
extend into the next bit period are causes of ISI. Unfortunately, there
is no equation for this since we are working with waves. The best
I can quantify is something like this:
3) Timing jitter due to residual previous period overshoot =
settling limit / slew rate
where the settling limit is defined to be the absolute value of
continued ringing above and below the dc final value
of the bus (Vhigh or Vlow), at the signal bit switching point.
Thus, on high speed busses, we try to terminate the bus correctly,
not drive too hard or too fast to reduce this ISI settling jitter. If
we don't do our signal integrity job correctly, then the bus
rings like a "mother" and ISI extends the bit periods out to larger
than necessary. An example of this is the PCI bus where
reflected wave switching causes excessive ISI.
On the other hand, it is possible to over dampen the rising and falling
edge waveforms on a driver for a given bit period. In this case
the edge does not reach the final dc stable operating point prior
to the next bit transition period. This can be used to our advantage
on repetitive waveforms, such as clocks, and non-baseband
encoded waveforms, like ethernet, fiber channel, and others,
where there is no dc component to the signal. Since the signal
is a band limited ac signal, eventually, after a number of periods,
the signal settles in and becomes symmetric around it's average
However, for a digital baseband signal, the average dc signal
level is data pattern dependent. If the slew rate of the signal
is lower than that necessary to fully transition from Vlow to
Vhigh, or Vhigh to Vlow, during one bit period, then the starting
point of the next signalling bit will be different than Vhigh or
Vlow and will induce bit to bit edge jitter. Here rise time and
knee frequency is a better indicator of ISI.
Fknee = 0.5 / Trise
Tknee = Trise/0.5
4) If Tknee > Tperiod then ISI due to waveform underdampening will
or Tpulse > Trise/0.5,
where Tpulse is the minimum sustainable pulse width without ISI.
For example, if a waveform has a rise time of 1ns, the shortest pulse width
that can be sustained without significant ISI is 2ns, equivalent to a frequency of
For a waveform with a rise time of 400ps, the shortest pulse width that can be
sustained without significant ISI is 800ps, equivalent to a frequency of
The rise time of a driven waveform rarely equals the received rise time
due to the frequency response of the transmission channel. In this case
the composite rise time can be calucuated as:
5) Tcomposite = SQRT(Trise(driver) **2 + (0.5/Tbandwidth) **2)
6) Tpulse > Tcomposite/0.5
This is the ISI usually seen in band limited communication channels
when the bandwidth of the channel is degraded. This is exactly what
happens when a transmission line on a pcb is loaded with the input
capicitance of devices. The frequency response of the transmission
channel rolls off, degrading the signal rise time, increasing the
effect of ISI.
Compared to these level shift and ISI effects, vias are generally
the least of my concerns. Keep 'em all the same. Keep the layer
transitions the same. Keep the numbers and positions on each net
the same and you reduce skew due to vias to sub 10ps levels.
The other skews due to level shift and ISI are generally
at least a magnitude or so greater.
"Dr. Edward P. Sayre" wrote:
> In out Gigabit and other high performance work, we see exactly the effects
> you mention, namely that the signal interconnects do not have the bandwidth
> to allow the transitions to reach their final logic level values. We have
> seen much baseline wandering in these circumstances. Our paper on Gigabit
> cabling and equalization shows this clearly - its on our web site.
> At 400 MHz, the effects are usually from improper termination and
> reflections which cause effects which look exactly the same on an
> eye-diagram but the causes are entirely different. Via inductance or
> capacitances are usually not the dominant effect.
> We have found that the CAE vendors are NOT a good place to start to
> understand these effects. They are basic to digital signal circuit and
> interconnect theory and can be evaluated entirely apart from a CAE product.
> A SPICE simulation package is always useful in these circumstances.
> ed sayre
> PS: Do you have an analytic expression for Intersymbol Interference (ISI)
> which is valid for serial digital signal streams?
> If not, do you have a good reference to ISI?
> At 08:55 AM 12/1/98 -0800, you wrote:
> >I have discovered in doing similar 400 Mhz simulations
> >with ps timing margins on a source synchronous bus, that
> >the big issue is usually Intersymbol Interference (ISI). Designers
> >that come at signal integrity from the communications theory
> >world are well aware of ISI on signal timing (jitter) behavior.
> >Designers that come at signal integrity from the digital design
> >world tend to forget, or not know, that we are working with
> >baseband signals that can have significant data dependent
> >DC offset shifts which will effect timing jitter.
> >At 400Mhz it is often the case that a waveform does not
> >have enough time to reach it's DC final value. This can be due
> >to an over driven signal that rings and has an edge rate faster than
> >necessary for the frequency of the bus. It can also be due to a
> >signal that has an edge rate which is not quite fast enough for
> >the frequency of the bus. In either case, there is significant
> >edge jitter due which is dependent upon the data pattern being
> >transmitted. For example, send a pattern of 7 zeros and
> >a one and then 7 zeros. Compare the crossings at the timing
> >measurement point with a pattern of 7 ones, a zero, and then
> >7 ones. There will be a difference. I guarantee that this is
> >usually an order of magnitude greater than the error in modeling
> >via inductance.
> >I don't mean to minimize the necessity for simulation vendors to
> >model via structures correctly. I have advocated this with my
> >simulaton vendor often. More voices crying in the wilderness
> >always help. However, to CAD vendors it is usually money that
> >speaks. Tie the request to a tangible market, or PO, and things
> >will often change quickly.
> | NORTH EAST SYSTEMS ASSOCIATES, INC. |
> | ------------------------------------- |
> | "High Performance Engineering & Design" |
> | Dr. Ed Sayre e-mail: email@example.com |
> | NESA, Inc. http://www.nesa.com/ |
> | 636 Great Road Tel +1.978.897-8787 |
> | Stow, MA 01775 USA Fax +1.978.897-5359 |
-- ___________________________ Scott McMorrow Principal Engineer SiQual
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