Thanks for your comments. Please find my comments below:
On Jul 13, 9:38am, Jose Luis Gonzalez Jimenez wrote:
> Subject: Re: [SI-LIST] : Split vs. common chip busses
> Dear Mike,
>
> >Fellow si-listers:
>
> >
> >We are presently evaluating a package that will have low
> >inductance VSS path but a high inductance VDD path. With
> >common supplies on the chip we could use the core's VDD to VSS
> >capacitance to lower the AC impedance of the VDD supply
> >and thus reduce switching noise when switching from
> >LOW to HIGH.
> >
> This may be true only for internal (core) switching noise. However, the=
> internal capacitance doesn't help to reduce switching noise originated =
by
> the simulteneous switching of the output drivers because the load
> capacitance is external and the return current loop only comprises one =
of
> the two power buses in the chip, depending on the direction of switchin=
g.
Let us say for example we had four supplies on the chip: one VSS and
one VDD for the core, and one VSS and one VDD for the I/O. Now also
assume that each of these four supplies had equivalent paths from the
chip through the package and to a pcb. Neglecting any pcb supply
impedance, then we can assume that each supply sees about the same
equivalent inductance from the chip to a "clean" supply. Implied
in this assumption is that mutual coupling between supplies is weak
though I realize this is difficult to acheive in practice.
Given the scenario above, if one has a "magical" 1 farad ideal capacitor
between I/O VSS and VDD, then these supplies are the same for
time varying signals. Hence outputs should see about 1/2 the
effective inductance giving rise to 1/2 the switching noise. Also,
switching noise should be approximately the same for either HIGH
to LOW or LOW to HIGH transitions as long as the buffers are
well balanced.
Furthermore if common core and I/O supplies are tied together one
should obtain another 1/2 drop in inductance and subsequent switching
noise. The core will always see the same VDD to VSS, although these
will move together from the pcb VDD and VSS depending on the
output driver switching patterns.
Of course, you won't have a 1 farad ideal capacitor and as you say
below, one much evaulate the amount of noise that would be generated
at the core by the I/O to see if the core can tolerate sharing
VSS and VDD with the I/O.
> This is one of the reasons why separated supply terminals are used for
> output drivers and core logic. Internal capacitance reduces only core l=
ogic
> switching noise. The switching noise of the output drivers cannot be
> reduced by adding on-chip capacitance. It only can be reduced by design=
ing
> propoerly the output driver itself. You may estimate the amount of nois=
e
> generated in the wors case output transition and calculate if it is
> tolerable by the core logic. Then, you could use the same power supply =
for
> both core and periphery.
>
> Jose Luis Gonz=E1lez
>
> _______________________________________________________________________=
_____
>
> O O O Departament
> O O O d'Enginyeria
> O O O Electronica
> U P C
>
> Departament d'Enginyeria Electronica
> UNIVERSITAT POLITECNICA DE CATALUNYA (UPC)
> Modul C4, Campus Nord
> c/. Gran Capita s/n 08034 BARCELONA (Spain)
> telf. + 34 3 4016748
> + 34 3 4017476
> fax. + 34 3 4016756
> email. [email protected]
> web: http://www-eel.upc.es
> _______________________________________________________________________=
____
>
>
>-- End of excerpt from Jose Luis Gonzalez Jimenez
-- =
_______________________________________________________________
Mike Degerstrom Email: [email protected]=
du =
Mayo Clinic - Gugg. Bldg. RM 1011-B Phone: (507) 284-3292
Rochester, MN 55905 FAX: (507) 284-9171
WWW: http://www.mayo.edu/sppdg/sppdg_home_page.html
_______________________________________________________________