RE: [SI-LIST] : bypass cap question (long, simple)
Peterson, James F (email@example.com)
Sat, 31 Jan 1998 12:19:23 -0500
I have worried and wondered about this issue before (the impact on
impedance & return paths caused by the trace jumping to another layer
with a different reference plane). Lawrence's input sounds intuitive
and, if correct, I believe it makes a good case for allowing for
adjacent layering of vcc/gnd planes in a stackup (if done correctly this
should provide a very effective capacitor at high frequencies and thus a
low impedance path for the return currents).
Honeywell Space Systems
> From: Haruny Said[SMTP:firstname.lastname@example.org]
> Sent: Saturday, January 31, 1998 11:05 AM
> To: Lawrence Butcher; si-list@silab.Eng.Sun.COM
> Cc: Lawrence.Butcher@Eng.Sun.COM
> Subject: Re: [SI-LIST] : bypass cap question (long, simple)
> after I read you message a couple of times I decided what you said
> make sense. I look at the problem as follows:
> You are connecting two transmission lines together, one side of the
> lines are connected by the via, the other side of the lines are
> via the inter-plane capacitance, Ci, between the power, ground and
> This connection will cause an impedance mismatch because Ci will be
> series with the two lines. For the sake of argument let's say you want
> keep the mismatch within 10% of the characteristic impedance of the
> If the capacitive impedance of Ci at the low frequency is more than
> 10% of
> Zo then you need to add a capacitor at the via. Otherwise a capacitor
> I would choose the capacitor as follows: the capacitor's impedance
> into account series L and R etc) in parallel with Ci would need to be
> than 10% of Zo at the low and high frequencies, and in your example I
> take the high frequency as being 500MHz - 1GHz, i.e. 5 - 10X 100MHz.
> To calculate Ci I would take into account the area around the via
> is given by the propagation time that is equivalent to the rise time
> of the
> The 10% is plucked out of the air, the value you choose would depend
> how much mismatch your design can tolerate.
> If there are 40 wires then it gets a little more complex, it
> depends on
> how the wires are placed but I think the same argument still applies.
> Does this make sense, or does anybody strongly disagree? I know there
> is a
> lot of rule-of-thumb in this answer but I don't think there is a
> If you want I can sketch something on paper to make it clearer and
> fax it
> to you.
> At 12:58 AM 1/31/98 -0800, Lawrence Butcher wrote:
> >Imagine that I build a 4 layer board. Imagine that there were two
> chips on
> >it, labeled U1 and U2. Imagine that I route the board strictly
> >style. All horizontal wires are on top above the ground plane, and
> >vertical wires are on the bottom below the power plane.
> > _______________
> > | |
> > | U1 ------* |
> > | | |
> > | | |
> > | | |
> > | U2 |
> > |_______________|
> >Normally, I would put bypass caps under U1 and bypass caps under U2.
> >I would cosy them up so that there was minimum distance between the
> >caps and the power supply pins on the chip.
> >Consider the image currents running on the power and ground planes.
> >An image current will sit directly under each wire. But that current
> >will have a hard time following the wire through the via, because it
> >would have to hop from the ground plane to the power plane.
> >It seems clear that a capacitor might be needed at that via site to
> >give the current in one plane a chance to hop to the other. Even
> >though there are no components nearby.
> >Intuition rarely substitutes for calculation. Question: Is this
> >How much capacitance? How does that vary if there are 40 wires
> >of 1? How does the number change with frequency?
> >The above illustrates a real problem. I am building an 8-layer
> >with a tentative stackup of:
> >1 Horizontal
> >2 GND Plane
> >3 V33 Plane
> >4 Vertical
> >5 Horizontal
> >6 V5 Plane
> >7 GND Plane
> >8 Vertical
> >My component placement places all of the 3 volt components above the
> >midline of the board, and all of the 5 volt components below the
> >Therefore, there are NO bypass caps from the 5V plane to ground in
> >top half of the board, and NO bypass caps from the 3.3V plane to
> >in the bottom half of the board.
> >A trace running horizontally on layer 5 in the top half of the board
> >will have an image current running on the V5 plane, and that current
> >has no way to get to the ground plane at a via site. Same for traces
> >running on layer 4 in the botton half of the board.
> >I want to add about 1 cap per square inch (about 50 more bypass
> >Half will be between V5 and ground in the top half of the board, and
> >will between V33 and ground in the bottom half of the board.
> >These components are there only to deal with my paranoia about image
> >currents. They would be placed even though there are already tons of
> >bypass caps in the same area, but exclusively to only one power
> >My coworkers have doubts. They especially don't like 50 more caps
> >there are no nearby chips connected to the power planes I am
> concerned with.
> >Most of my signals are changing at 100 MHz, but there is a bunch of
> 33 MHz
> >activity running around. (Fast, for me).
> >Is this a non-existent problem, or a real one? Comments?
> Haruny Said
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