When I run the numbers though the tool I use I come up with about 58
ohms. (Eagleware =TLINE=) <http://www.eagleware.com/> I believe PCB
designers spend too much time converting PCB geometric parameters to an
impedance. A PCB designer should be more concerned with the value of the
line and its tolerance i.e. 50 ohms +/- 10%, which reputable vendors
regularly achieve. Many tools today are accurate enough to put you in
the ball park. Once there, find a vendor capable of handling controlled
impedance traces. Supply the vendor with your dimensions you may have to
alter yours to match.
The point of the calculation is to come up with copper and dielectric
dimensions that achieve both the electrical (Zo, Xtalk and insertion
loss) and physical parameters ( maximum and minimum track width, spacing
and board thick). Give the PCB vendor the latitude to alter the track
width and dielectric dimensions to meet your design needs. To aid the
PCB vendor do not use minimum or maximum dimensions i.e. the minimum
track width say is 5 mils. Use 6, this gives the vendor the opportunity
to increase or decrease the track width in order to meet your impedance
requirements. In this case if minimum spacing was used the increased
track width would create spacing violations. So then, make sure the
decreased spacing does not adversely effect coupling. (that dimension
would have been another minimum)
Many factors effect the calculated impedance, particularly for
microstrip and the only true way to confirm the numbers is by taking a
cross section of the PCB in question and measure the dimensions. This is
another feature of a reputable vendor.
Typical variations on the dimensions used:
The trace is actually a trapezoid, with about a 0.001 difference between
top and bottom.
The trace can vary +/- 0.001
The dielectric spacing varies +/- 0.001
In FR 4 Er varies 4.7 to 3.8, 1 MHz to 1 GHz respectively
The trace thickness +/- 0.0003 for stripline
The trace thickness over 0.001 above weight. (plating) for microstrip
Some of the effects of the variations can be minimized by using wider
traces and thicker dielectrics, layout permitting.
Chris Knapton
Cambrian System Corporation
-----Original Message-----
From: casperdd [mailto:Dominic.Casperson@cern.ch]
Sent: Thursday, August 20, 1998 5:15 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Trace impedance
Hi
I was hoping that someone might be able to shed a little
light on a
problem that I have encountered regarding the impedance
of stripline,
and microstrip PCB tracks.
I require a formula that is capable of predicting the
impedance's of
stripline, and microstrip tracks. I have already found
several from
different source, but none of them seem to agree with
each other, my TDR
results, or the TDR results from "MECL system design
handbook" by
Motorola. All the formulas that I have come across claim
to have an
accuracy to within about 5%, but as far as I can tell
the discrepancy
can reach up to 20%, depending on the dimensions
involved.
The region of interest to me is:
Track width = 10 mils
Track thickness = 1.37 mils
Ground plane/Track separation (dielectric height) = 8
mils
Relative permittivity = 4.7
TDR edge rise time = 28ps
The most alarming problem that I have encountered is the
natural
logarithm that most formula seem to have, this then
returns a negative
number when its argument is smaller than one, even
though most formula
claim to still be accurate at this limit.
I would appreciate it if anyone could show me where I
have been going
wrong, or point me in the direction of an accurate
formula.
Many Thanks
Dominic Casperson
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